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參數(shù)資料
| 型號(hào)： | SN74ABT3612PQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CABLE ASSEMBLY; N MALE TO N FEMALE; 50 OHM, RG393/U COAX, DOUBLE SHIELDED |
| 中文描述： | 64】36】2時(shí)鐘雙向先入先出存儲(chǔ)器 |
| 文件頁數(shù)： | 1/31頁 |
| 文件大?。?/td> | 462K |
| 代理商： | SN74ABT3612PQ |
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SN74ABT3612
64
×
36
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Two Independent 64
×
36 Clocked FIFOs
Buffering Data in Opposite Directions
Mailbox-Bypass Register for Each FIFO
Programmable Almost-Full and
Almost-Empty Flags
Microprocessor Interface Control Logic
EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
Passive Parity Checking on Each Port
Parity Generation Can Be Selected for Each
Port
Low-Power Advanced BiCMOS Technology
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 10 ns
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64
×
36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is
stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each
port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or
more devices can be used in parallel to create wider datapaths.
The SN74ABT3612 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock
that writes data to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are
two-stage synchronized to the port clock that reads data from its array.
The SN74ABT3612 is characterized for operation from 0
°
C to 70
°
C.
For more information on this device family, see the following application reports:
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number
SCAA007)
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
MetastabilityPerformance of Clocked FIFOs (literature number SCZA004)
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
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