參數(shù)資料
型號： SN74ABT3613PQ
廠商： Texas Instruments, Inc.
英文描述： 64 】 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
中文描述： 64】36成績第一的，在總線匹配和字節(jié)交換先出存儲器
文件頁數(shù)： 1/32頁
文件大?。?/td> 460K
代理商： SN74ABT3613PQ
SN74ABT3613
64
×
36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128F – JULY 1992 – REVISED APRIL 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Low-Power Advanced BiCMOS Technology
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
64
×
36 FIFO Buffering Data From Port A to
Port B
Mailbox-Bypass Registers in Each
Direction
Dynamic Port-B Bus Sizing of 36 Bits (Long
Word), 18 Bits (Word), and 9 Bits (Byte)
Selection of Big- or Little-Endian Format for
Word and Byte Bus Sizes
Three Modes of Byte-Order Swapping on
Port B
Programmable Almost-Full and
Almost-Empty Flags
Microprocessor Interface Control Logic
FF and AF Flags Synchronized by CLKA
EF and AE Flags Synchronized by CLKB
Passive Parity Checking on Each Port
Parity Generation Can Be Selected for Each
Port
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 10 ns
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Quad Flat
(PQ) Packages
description
The SN74ABT3613 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read-access times as fast as 10 ns. A 64
×
36 dual-port SRAM FIFO in this device buffers
data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags
(almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO data on
port B can be output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three
modes of byte-order swapping are possible with any bus-size selection. Communication between each port can
bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has
been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can
be selected for data read from each port.
The SN74ABT3613 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses controlled by a synchronous interface.
The full flag (FF) and almost-full (AF) flag of a FIFO are two-stage synchronized to the port clock that writes data
to its array. The empty flag (EF) and almost-empty (AE) flag of a FIFO are two-stage synchronized to the port
clock that reads data from its array.
The SN74ABT3613 is characterized for operation from 0
°
C to 70
°
C.
For more information on this device family, see the following application reports:
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications
(literature number SCAA014)
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
Internetworking the SN74ABT3614(literature number SCAA018)
MetastabilityPerformance of Clocked FIFOs(literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
相關PDF資料
PDF描述
SN74ABT3614PCB 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
SN74ABT3614PQ 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
SN74ABT38543 36-Bit Registered Transceivers With 3-State Outputs(36位記錄收發(fā)器(三態(tài)輸出))
SN74ABT38652 36-Bit Bus Transceivers And Registers With 3-State Outputs(36位總線收發(fā)器和寄存器(三態(tài)輸出))
SN74ABT541BDB OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
相關代理商/技術參數(shù)
參數(shù)描述
SN74ABT3614 制造商:TI 制造商全稱:Texas Instruments 功能描述:64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
SN74ABT3614-15PCB 功能描述:先進先出 64 x 36 x 2 bidir Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ABT3614-15PQ 功能描述:先進先出 64 x 36 x 2 bidir Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ABT3614-20PCB 功能描述:先進先出 64 x 36 x 2 bidir Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ABT3614-20PQ 功能描述:先進先出 64 x 36 x 2 bidir Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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