參數(shù)資料
型號: SN65HVD
廠商: Texas Instruments, Inc.
英文描述: 3.3-V RS-485 Transceivers(3.3V,RS-485收發(fā)器)
中文描述: 3.3V的RS - 485收發(fā)器(3.3V,RS - 485接口收發(fā)器)
文件頁數(shù): 6/19頁
文件大小: 142K
代理商: SN65HVD
SN65HVD10,SN65HVD10Q,SN75HVD10
SN65HVD11,SN65HVD11Q,SN75HVD11
SN65HVD12,SN75HVD12
SLLS505E
FEBRUARY 2002
REVISED NOVEMBER 2002
www.ti.com
6
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
12.5
TYP(1)
MAX
25
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
HVD10
20
ns
Propagation delay time, high-to-low-level output
HVD10
12.5
20
25
tPLH
Propagation delay time, low-to-high-level output
HVD11
HVD12
VID =
1.5 V to 1.5 V,
CL = 15 pF, See Figure 8
1 5 V t 1 5 V
30
55
70
ns
tPHL
Propagation delay time, high-to-low-level output
HVD11
HVD12
30
55
70
ns
HVD10
1.5
tsk(p)
tsk( )
Pulse skew (|tPHL tPLH|)
HVD11
4
ns
HVD12
4
HVD10
8
tsk(pp)(2)
Part-to-part skew
Part to art skew
HVD11
15
ns
)( )
HVD12
15
tr
tf
tPZH(1)
tPZL(1)
tPHZ
tPLZ
tPZH(2)
tPZL(2)
(1)All typical values are at 25
°
C and with a 3.3-V supply.
(2)tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Output signal rise time
CL = 15 pF, See Figure 8
15 pF See Figure 8
1
2
5
ns
Output signal fall time
1
2
5
Output enable time to high level
15
Output enable time to low level
CL = 15 pF, DE at 3 V,
CL = 15 F, DE at 3 V,
See Figure 9
15
ns
Output disable time from high level
20
Output disable time from low level
15
Propagation delay time, standby-to-high-level output
CL = 15 pF
CL = 15 F
,
DE at 0,
See Figure 10
6
Propagation delay time, standby-to-low-level output
6
μ
s
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