參數(shù)資料
型號: SN54ABT16648
廠商: Texas Instruments, Inc.
英文描述: 16-Bit Bus Transceivers and Registers With 3-State Outputs(16位總線收發(fā)器和寄存器(三態(tài)輸出))
中文描述: 16位總線收發(fā)器和寄存器具有三態(tài)輸出(16位總線收發(fā)器和寄存器(三態(tài)輸出))
文件頁數(shù): 1/7頁
文件大小: 157K
代理商: SN54ABT16648
SN54ABT16648, SN74ABT16648
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS213 – SEPTEMBER 1992 – REVISED OCTOBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1992, Texas Instruments Incorporated
3–1
Members of the Texas Instruments
Widebus
Family
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25
°
C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes
PCB Layout
High-Drive Outputs (–32-mA I
OH
,
64-mA I
OL
)
Packaged in Plastic 300-mil Shrink
Small-Outline Packages and 380-mil
Fine-Pitch Ceramic Flat Packages Using
25-mil Center-to-Center Spacings
description
The
ABT16648 is a 16-bit bus transceiver that
consists of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. The device can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the
ABT16648.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. The direction control (DIR) determines which bus will receive data when OE
is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in
the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT16648 is available in TI’s shrink small-outline package (DL), which provides twice the I/O pin
count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT16648 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74ABT16648 is characterized for operation from –40
°
C to 85
°
C.
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1DIR
1CLKAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
SN54ABT16648 . . . WD PACKAGE
SN74ABT16648 . . . DL PACKAGE
(TOP VIEW)
Widebus and EPIC-
ΙΙ
B are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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