參數(shù)資料
型號(hào)： SN54LVT8980
廠商： Texas Instruments, Inc.
英文描述： EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
中文描述： 嵌入式測(cè)試總線控制器IEEE標(biāo)準(zhǔn)1149.1 JTAG接口，8咨詢大師比特通用主機(jī)接口
文件頁(yè)數(shù)： 15/34頁(yè)
文件大小： 495K
代理商： SN54LVT8980
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 5. Command Register Decode
COMMAND
TEST OPERATION COMMENTS
BIT
GROUP
BIT
NO.
VALUE
RESULT
WORKING
TAP STATE
USES
COUNTER
USES
TDI
BUFFER
USES
TDO
BUFFER
SWRST
7
0
Normal operation
1
Full reset
TRST
6
0
If not in discrete-control mode, output high to TRST pin
1
If not in discrete-control mode, output low to TRST pin
00
Finish command in TAP state Test-Logic-Reset
ENDST
5 4
5–4
01
Finish command in TAP state Run-Test/Idle
10
Finish command in TAP state Pause-DR
11
Finish command in TAP state Pause-IR
0000
Null
0001
Reserved
0010
Execute run test
Run-Test/Idle
Yes
No
No
0011
Execute input-only ASP scan
N/A
Yes
Yes
No
0100
Execute ASP scan
N/A
Yes
Yes
Yes
0101
Execute output-only ASP scan
N/A
Yes
No
Yes
0110
Execute state move
N/A
No
No
No
OPCOD
3 0
3–0
0111
Execute state jump
N/A
No
No
No
1000
Execute instruction-register scan
Shift-IR
Yes
Yes
Yes
1001
Execute data-register scan
Shift-DR
Yes
Yes
Yes
1010
Execute input-only instruction-register scan
Shift-IR
Yes
Yes
No
1011
Execute input-only data-register scan
Shift-DR
Yes
Yes
No
1100
Execute output-only instruction-register scan
Shift-IR
Yes
No
Yes
1101
Execute output-only data-register scan
Shift-DR
Yes
No
Yes
1110
Execute recirculate instruction-register scan
Shift-IR
Yes
Yes
No
1111
Execute recirculate data-register scan
Shift-DR
Yes
Yes
No
The software-reset (SWRST) bit is provided to allow software initiation of full eTBC reset. This bit of the
command register can be written at any time, regardless of the configuration or command in progress. The
test-reset (TRST) bit allows direct software control of the state of TRST output in modes other than
discrete control.
The end-TAP-state (ENDST) bit group determines the TAP state in which the target scan chain is left when the
requested command finishes. The operation-code (OPCOD) bit group determines the test operation to be
executed in the target.
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