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參數資料
| 型號： | SN54LVT8980 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES |
| 中文描述： | 嵌入式測試總線控制器IEEE標準1149.1 JTAG接口，8咨詢大師比特通用主機接口 |
| 文件頁數： | 12/34頁 |
| 文件大小： | 495K |
| 代理商： | SN54LVT8980 |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register descriptions
A summary of the eTBC registers, their address mappings, bit assignments, reset values, and host accessibility
(read/write or read-only) is provided in Table 1. All registers are fully readable by the host. All registers are fully
writeable by the host with the exception of the status and TDI-buffer registers. Also, with the exception of
TDO-buffer and command registers, writes to any register while a command is in progress are held off (RDY
inactive) or ignored. Bits designated as reserved should be written to logic 0; read-only bits designated as
reserved always read logic 0.
Table 1. Register Summary
ADDRESS
A2–A0
REGISTER
REGISTER DETAIL
(BIT ASSIGNMENTS)
RESET
VALUE
HOST
ACCESS
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
000
ConfigurationA
Reserved
NTOE
LPBK
MODE
0x00
R/W
001
ConfigurationB
CDIV
Reserved
RDLY
0x80
R/W
010
Status
TDIS
TDOS
CTRS
Reserved
TAPST
0x00
R
011
Command
SWRST
NTRST
ENDST
OPCOD
0x00
R/W
100
TDO buffer
0x00
R/W
101
TDI buffer
0x00
R
110
Counter
0x00
R/W
111
Discrete control
Reserved
DNTR
DTMS
DTDI
DTDO
0x00
R/W
configuration registers
All eTBC test commands operate under the influence of the configurationA and configurationB registers. The
decodes of the various bit groups assigned to these registers are given in Table 2 and Table 3, respectively.
These registers are fully readable at all times and are fully writeable except when an eTBC command is in
progress. Bit group values designated as reserved should not be written.
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