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參數(shù)資料
| 型號(hào)： | SN54LVT652 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 中文描述： | 的3.3V ABT生根粉八路總線收發(fā)器和3冊(cè)態(tài)輸出 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大小： | 179K |
| 代理商： | SN54LVT652 |
SN54LVT652, SN74LVT652
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS141E – MAY 1992 – REVISED JULY 1995
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore,
when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE
should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the
current-sourcing capability of the driver.
The SN74LVT652 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT652 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74LVT652 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
L
OEBA
H
CLKAB
H or L
↑
↑
↑
H or L
↑
X
CLKBA
H or L
↑
H or L
↑
↑
↑
X
SAB
X
SBA
X
A1–A8
Input
B1–B8
Input
Isolation
L
H
X
X
Input
Input
Store A and B data
X
H
X
X
X
Input
Unspecified
Store A, hold B
H
H
X
Input
Output
Store A in both registers
L
X
X
X
X
Unspecified
Input
Hold A, store B
L
L
X
Output
Input
Store B in both registers
L
L
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.
Select control = L; clocks can occur simultaneously
Select control = H; clocks must be staggered in order to load both registers
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