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參數(shù)資料
| 型號(hào)： | SN54GTL16616WD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 17-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS |
| 中文描述： | 17位LVTTL-TO-GTL/GTL通用總線收發(fā)器與緩沖時(shí)鐘輸出 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | SN54GTL16616WD |
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
Universal Bus Transceiver (UBT
)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
GTL Buffered CLKAB Signal (CLKOUT)
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
Equivalent to ’16601 Function
I
off
Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Distributed V
CC
and GND-Pin Configuration
Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Ceramic Flat
(WD) Packages
description
The ’GTL16616 devices are 17-bit universal
bus
transceivers
(UBTs)
LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
signal-level translation. They combine D-type
flip-flops and D-type latches to allow for transparent, latched, clocked, and clocked-enabled modes of data
transfer identical to the ’16601 function. Additionally, they provide for a copy of CLKAB at GTL/GTL+ signal
levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). The devices provide an
interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels.
Higher-speed operation is a direct result of the reduced output swing (
<
1 V), reduced input threshold levels, and
output edge control (OEC
).
that
provide
The user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or the preferred
higher noise margin GTL+ (V
TT
= 1.5 V and V
REF
= 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
REF
is the reference input voltage for the B port. V
CC
(5 V) supplies the internal and GTL circuitry while
V
CC
(3.3 V) supplies the LVTTL output buffers.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, OEC, and UBT are trademarks of Texas Instruments Incorporated.
SN54GTL16616 . . . WD PACKAGE
SN74GTL16616 . . . DGG OR DL PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
V
CC
(3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
(3.3 V)
A16
A17
GND
CLKIN
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
V
CC
(5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
CLKOUT
CLKBA
CEBA
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