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參數(shù)資料
| 型號(hào)： | SN54ALS1020A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual 4-Input Positive-Nand Gates(雙4輸入正與非門) |
| 中文描述： | 雙路4輸入正和非門（雙4輸入正與非門） |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 49K |
| 代理商： | SN54ALS1020A |
SN54ALS1020A, SN74ALS1020A
DUAL 4-INPUT POSITIVE-NAND BUFFERS
SDAS 242 – D2661, APRIL 1982 – REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS
77251–1443
Copyright
1986, Texas Instruments Incorporated
5BASIC
1
Buffer Version of ’ALS20B
Package Options include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent 4-input
NAND buffers. They perform the Boolean
functions Y = A
B
C
B or Y = A+B+C+D positive
logic.
The SN54ALS1020A is characterized for opera-
tion over the full military temperature range of
–55
°
C to 125
°
C. The SN74ALS1020A is
characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLE
(each gate)
INPUTS
B
C
H
H
X
X
L
X
X
L
X
X
OUTPUT
Y
L
H
H
H
H
A
H
L
X
X
X
D
H
X
X
X
L
logic symbol
1A
1
1B
2
5
1D
4
1C
6
1Y
2Y
8
&
2A
9
2B
10
13
2D
12
2C
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
1A
1B
1C
1D
1Y
2Y
2A
2B
2C
2D
logic diagram (positive logic)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
NC
1C
1D
1Y
GND
V
CC
2D
2C
NC
2B
2A
2Y
SN54ALS1020A . . . J PACKAGE
SN74ALS1020A . . . D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2C
NC
NC
NC
2B
NC
NC
1C
NC
1D
SN54ALS1020A . . . FK PACKAGE
(TOP VIEW)
1
1
N
2
2
1
G
N
NC – No internal connection
C
V
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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