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參數(shù)資料
| 型號： | SN54ALS114A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual J-K Negative-Edge-Triggered Flip-Flop With Clear and Preset(雙下降沿J-K觸發(fā)器(帶預(yù)置,消除和時(shí)鐘)) |
| 中文描述： | 雙JK負(fù)沿觸發(fā)器具有明確和預(yù)設(shè)（雙下降沿JK觸發(fā)器（帶預(yù)置，消除和時(shí)鐘）跳高） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 70K |
| 代理商： | SN54ALS114A |
SN54ALS114A, SN74ALS114A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1986, Texas Instruments Incorporated
5BASIC
1
Fully Buffered to Offer Maximum isolation
from External Disturbance
Package Options include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Typical Maximum Clock Frequency
30 MHz
Typical Power Dissipation per Flip-Flop
6 mW
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other inputs.
When Preset and Clear are inactive (high), data at
the J and K inputs meeting the setup time
requirements are transferred to the outputs on the
negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
The SN54ALS114A is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The SN74ALS114A is characterized for
operation from 0
°
C to 70
°
C.
FUNCTION TABLE
INPUTS
CLK
X
X
X
↓
↓
↓
↓
H
OUTPUTS
Q
H
L
H
Q0
H
L
TOGGLE
Q0
PRE
L
H
L
H
H
H
H
H
The output levels in this configuration are not guaranteed to
meet the minimum levels for VOH if the lows at Preset and
Clear are near VIL maximum. Furthermore, this configuration
is nonstable; that is, it will not persist when either Preset or
Clear returns to its inactive (high) level.
CLR
H
L
L
H
H
H
H
H
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Q
L
H
H
Q0
L
H
Q0
logic symbol
Pin numbers are for D, J, and N packages.
1Q
1Q
2Q
2Q
8
9
6
5
R
1K
C1
1J
S
12
2K
10
2PRE
13
CLK
11
2J
2
1K
1
CLR
3
1J
1PRE
4
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CLR
1K
1J
1PRE
1Q
1Q
GND
V
CC
CLK
2K
2J
2PRE
2Q
2Q
SN54ALS114A . . . J PACKAGE
SN74ALS114A . . . D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2K
NC
2J
NC
2PRE
1J
NC
1PRE
NC
1Q
SN54ALS114A . . . FK PACKAGE
(TOP VIEW)
1
1
N
2
2
C
1
G
N
V
NC–No internal connection
This symbol is in accordance with ANSI/IEEE Std 911-1984 and
IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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