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參數(shù)資料
| 型號： | SN54ALS113A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual J-K Negative-Edge-Triggered Flip-Flop With Preset(雙下降沿J-K觸發(fā)器(帶預(yù)置)) |
| 中文描述： | 雙JK負(fù)沿觸發(fā)器與預(yù)置觸發(fā)器（雙下降沿JK觸發(fā)器（帶預(yù)置）） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 68K |
| 代理商： | SN54ALS113A |
SN54ALS113A, SN74ALS113A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET
SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1986, Texas Instruments Incorporated
5BASIC
1
Fully Buffered to Offer Maximum isolation
from External Disturbance
Package Options Include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Dependable Texas Instruments Quality and
Reliability
TYPE
TYPICAL MAXIMUM
CLOCK FREQUENCY
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
6 mW
’ALS113A
40 MHz (CL=15 pF)
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset input sets the outputs regardless of the
levels of the other inputs. When Preset PRE is
inactive (high), data at the J and K inputs meeting
the setup time requirements are transferred to the
outputs on the negative-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the fall time of the
clock pulse. Following the hold time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by tying
J and K high.
The SN54ALS113A is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The SN74ALS113A is characterized for
operation from 0
°
C to 70
°
C.
FUNCTION TABLE
INPUTS
CLK
J
X
X
↓
L
↓
H
↓
L
↓
H
H
X
OUTPUTS
Q
H
Q0
H
L
TOGGLE
Q0
PRE
L
H
H
H
H
H
K
X
L
L
H
H
X
Q
L
Q0
L
H
Q0
1Q
1Q
2Q
2Q
8
9
6
5
1K
C1
1J
S
12
2K
10
2PRE
13
2CLK
11
2J
2
1K
1
1CLK
3
1J
1PRE
4
logic symbol
NC–No internal connection
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2K
NC
2J
NC
2PRE
1J
NC
1PRE
NC
1Q
SN54ALS113A . . . FK PACKAGE
(TOP VIEW)
1
1
N
2
2
2
1
G
N
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1 CLK
1K
1J
1PRE
1Q
1Q
GND
V
CC
2CLK
2K
2J
2PRE
2Q
2Q
SN54ALS113A . . . J PACKAGE
SN74ALS113A . . . D OR N PACKAGE
(TOP VIEW)
V
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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