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| 型號： | SN54ABT3614HFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING |
| 中文描述： | 64】36】2時鐘雙向第一的，在總線匹配和字節(jié)交換先出存儲器 |
| 文件頁數(shù)： | 39/42頁 |
| 文件大小： | 646K |
| 代理商： | SN54ABT3614HFP |
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SN54ABT3614
64
×
36
×
2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 30 pF (see Figures 4 through 27)
PARAMETER
MIN
MAX
UNIT
fmax
ta
tpd(C-FF)
tpd(C-EF)
tpd(C-AE)
tpd(C-AF)
50
MHz
Access time, CLKA
↑
to A0–A35 and CLKB
↑
to B0–B35
Propagation delay time, CLKA
↑
to FFA and CLKB
↑
to FFB
Propagation delay time, CLKA
↑
to EFA and CLKB
↑
to EFB
Propagation delay time, CLKA
↑
to AEA and CLKB
↑
to AEB
Propagation delay time, CLKA
↑
to AFA and CLKB
↑
to AFB
Propagation delay time, CLKA
↑
to MBF1 low or MBF2 high and
CLKB
↑
to MBF2 low or MBF1 high
Propagation delay time, CLKA
↑
to B0–B35 and CLKB
↑
to A0–A35
Propagation delay time, CLKB
↑
to PEFB
Propagation delay time, MBA to A0–A35 valid and SIZ1, SIZ0 to B0–B35 valid
2
12
ns
2
12
ns
2
12
ns
2
12
ns
2
12
ns
tpd(C-MF)
1
12
ns
tpd(C-MR)
tpd(C-PE)§
tpd(M-DV)
tpd(D-PE)
tpd(O-PE)
tpd(O-PB)
3
13
ns
2
12
ns
1
11.5
ns
Propagation delay time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
3
12.5
ns
Propagation delay time, ODD/EVEN to PEFA and PEFB
3
14
ns
Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35)
2
12
ns
tpd(E-PE)
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1,
SIZ0, or PGB to PEFB
1
23
ns
tpd(E-PB)
Propagation delay time, MBA or PGA to parity bits (A8, A17, A26, A35); SIZ1, SIZ0, or PGB to
parity bits (B8, B17, B26, B35)
3
19
ns
tpd(R-F)
Propagation delay time, RST to (MBF1, MBF2) high
1
20
ns
ten
Enable time, CSA and W/RA low to A0–A35 active and
CSB low and W/RB high to B0–B35 active
2
12
ns
tdis
Disable time, CSA or W/RA high to A0–A35 at high impedance and
CSB high or W/RB low to B0–B35 at high impedance
Writing data to the mail1 register when the B0–B35 outputs are active and SIZ1, SIZ0 are high
Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high
§Applies only when a new port-B bus size is implemented by the rising CLKB edge
Applies only when reading data from a mail register
1
9
ns
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