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參數(shù)資料
| 型號： | SN54ABT3614HFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING |
| 中文描述： | 64】36】2時(shí)鐘雙向第一的，在總線匹配和字節(jié)交換先出存儲器 |
| 文件頁數(shù)： | 10/42頁 |
| 文件大?。?/td> | 646K |
| 代理商： | SN54ABT3614HFP |
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SN54ABT3614
64
×
36
×
2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full–1, or almost full–2. The almost-full state is defined by the value of
the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during
a device reset (see reset). An almost-full flag is low when the FIFO contains (64 – X) or more long words in
memory and is high when the FIFO contains [64 – (X + 1)] or fewer long words.
Two low-to-high transitions of the almost-full-flag synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 – (X + 1)]
or fewer words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced
the number of long words in memory to [64 – (X + 1)]. An almost-full flag is set high by the second low-to-high
transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to
[64 – (X + 1)]. A low-to-high transition of an almost-full-flag synchronizing clock begins the first synchronization
cycle if it occurs at time t
sk2
, or greater, after the read that reduces the number of long words in memory to
[64 – (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 19 and 20).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB
writes B0–B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0
and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted
writes to a mail register are ignored while the mail flag is low.
When the port-A data outputs (A0–A35) are active, the data on the bus comes from the FIFO2 output register
when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0–B35) are
active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are
low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high
by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB and both port-B bus-size select
(SIZ1 and SIZ0) inputs are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A
read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after
it is read and changes only when new data is written to the register.
dynamic bus sizing
The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1
or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big
endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and
synchronous to CLKB to communicate with peripherals of various bus widths.
The levels applied to SIZ0 and SIZ1 and the big-endian select (BE) input are stored on each CLKB low-to-high
transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to
Figure 1.
Only 36-bit long-word data is written to or read from the two FIFO memories on the SN54ABT3614.
Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2
RAM. Port-B bus sizing does not apply to mail-register operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54ABT3614PCB | 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING |
| SN54ABT373FK | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT373J | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT373W | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN74ABT373DB | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54ABT3614PCB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING |
| SN54ABT373 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT373_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT373FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT373J | 制造商:Texas Instruments 功能描述: 制造商:TEXAS INSTRUMENTS INC 功能描述: |
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