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參數(shù)資料
| 型號： | SN54ABT3614PCB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING |
| 中文描述： | 64】36】2時鐘雙向第一的，在總線匹配和字節(jié)交換先出存儲器 |
| 文件頁數(shù)： | 1/42頁 |
| 文件大小： | 646K |
| 代理商： | SN54ABT3614PCB |
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SN54ABT3614
64
×
36
×
2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Two Independent 64
×
36 Clocked FIFOs
Buffering Data in Opposite Directions
Mailbox-Bypass Register for Each FIFO
Dynamic Port-B Bus Sizing of 36 Bits (Long
Word), 18 Bits (Word), and 9 Bits (Byte)
Selection of Big- or Little-Endian Format for
Word and Byte Bus Sizes
Three Modes of Byte-Order Swapping on
Port B
Almost-Full and Almost-Empty Flags
Microprocessor Interface Control Logic
EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
Passive Parity Checking on Each Port
Parity Generation Can Be Selected for Each
Port
Low-Power Advanced BiCMOS Technology
Supports Clock Frequencies up to 50 MHz
Fast Access Times of 12 ns
Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9560901QYA
and 5962-9560901NXD
Package Options Include 132-Pin Ceramic
Quad Flat (HFP) and 120-Pin Plastic Quad
Flat (PCB) Packages
description
The SN54ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 50 MHz and has read-access times as fast as 12 ns. Two independent 64
×
36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost full and almost empty) to indicate when a selected number of words is
stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice
of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size
selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port
and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its
array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads
data from its array.
The SN54ABT3614 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
Copyright
2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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