參數(shù)資料
型號(hào)： SN54ABT3614PCB
廠商： Texas Instruments, Inc.
英文描述： 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
中文描述： 64】36】2時(shí)鐘雙向第一的，在總線匹配和字節(jié)交換先出存儲(chǔ)器
文件頁(yè)數(shù)： 12/42頁(yè)
文件大小： 646K
代理商： SN54ABT3614PCB
SN54ABT3614
64
×
36
×
2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
B17
B35
B26
B17
2nd: Read From FIFO1/Write to FIFO2
B35
B26
B17
3rd: Read From FIFO1/Write to FIFO2
(e) BYTE SIZE – LITTLE ENDIAN
4th: Read From FIFO1/Write to FIFO2
1st: Read From FIFO1/Write to FIFO2
B35
B27
B17
B9
B8
B0
B9
B8
B0
B27
B9
B8
B0
B27
B9
B8
B0
D
C
B
A
H
H
L
BE
SIZ1
SIZ0
Figure 1. Dynamic Bus Sizing (Continued)
bus-matching FIFO1 reads
Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B,
only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the
long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size
implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 1.
Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its
output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIFO1
read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread
long-word data.
When reading data from FIFO1 in byte or word format, the unused B0–B35 outputs remain inactive but static
with the unused FIFO1 output register bits holding the last data value to decrease power consumption.
bus-matching FIFO2 writes
Data is written to the FIFO2 RAM in 36-bit long-word increments. FIFO2 writes, with a long-word bus size,
immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner
shown in Figure 1.
Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from
the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write
before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data.
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