參數(shù)資料
型號: SN54ABT32500
廠商: Texas Instruments, Inc.
英文描述: 36-Bit Universal Bus Transceivers With 3-State Outputs(36位通用總線收發(fā)器(三態(tài)輸出))
中文描述: 36位通用總線收發(fā)器與三態(tài)輸出(36位通用總線收發(fā)器(三態(tài)輸出))
文件頁數(shù): 5/8頁
文件大?。?/td> 135K
代理商: SN54ABT32500
SN54ABT32500, SN74ABT32500
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS462 – JUNE 1992–REVISED OCTOBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ABT32500
MIN
TYP
SN74ABT32500
MIN
TYP
UNIT
MAX
–1.2
MAX
–1.2
VIK
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
IOH = –3 mA
IOH = –24 mA
IOH = –32 mA
IOL = 48 mA
IOL = 64 mA
V
VOH
2.5
2.5
V
3
2
3
2
VOL
0.55
0.55
0.55
±
1
±
100
V
II
Control inputs
A or B ports
VCC= 5 5 V
VCC = 5.5 V,
VI= VCCor GND
VI = VCC or GND
μ
A
Ihold
A or B ports
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 0,
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.8 V
VI = 2 V
VO = 2.7 V
VO = 0.5 V
VI or VO
4.5 V
VO = 5.5 V
VO = 2.5 V
100
μ
A
IOZH
IOZL
IOFF
ICEX
IO§
50
μ
A
μ
A
μ
A
μ
A
mA
–50
±
100
50
–180
Outputs high
–50
–100
VCC= 5 5 V
VCC = 5.5 V,
VI= VCCor GND
VI = VCC or GND
IO= 0
IO = 0,
Outputs high
Outputs low
Outputs disabled
2
ICC
60
0.5
mA
ICC
VCC = 5.5 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
One input at 3.4 V,
1
mA
Ci
Cio
All typical values are at VCC = 5 V, TA = 25
°
C.
The parameters IOZH and IOZL include the input leakage current.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Control inputs
A or B ports
pF
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT32500
MIN
SN74ABT32500
MIN
UNIT
MAX
MAX
fclock
Clock frequency
MHz
tw
Pulse duration
LE high
CLK high or low
A or B before CLK
A or B before LE
A or B after CLK
A or B after LE
ns
tsu
Setup time
ns
th
Hold time
ns
ABT32500–2
P
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