參數(shù)資料
型號(hào): SN54ABT32500
廠商: Texas Instruments, Inc.
英文描述: 36-Bit Universal Bus Transceivers With 3-State Outputs(36位通用總線收發(fā)器(三態(tài)輸出))
中文描述: 36位通用總線收發(fā)器與三態(tài)輸出(36位通用總線收發(fā)器(三態(tài)輸出))
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 135K
代理商: SN54ABT32500
SN54ABT32500, SN74ABT32500
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS462 – JUNE 1992–REVISED OCTOBER 1992
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 5 V, T
A
= 25
°
C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
High-Drive Outputs (–32-mA I
OH
,
64-mA I
OL
)
Packaged in 100-Pin Plastic Shrink Quad
Flat Pack (SQFP) With 14
×
14-mm Package
Body Using 0.5-mm Lead Pitch
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1992, Texas Instruments Incorporated
1
Members of the Texas Instruments
Widebus+
Family
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
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SN74ABT32500 . . . PZ PACKAGE
(TOP VIEW)
2A10
2A9
GND
2A8
2A7
2A6
2A5
GND
2A4
2A3
2A2
2A1
V
CC
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
1A8
GND
1A9
1A10
2B10
2B9
GND
2B8
2B7
2B6
2B5
GND
2B4
2B3
2B2
2B1
V
CC
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
1B8
GND
1B9
1B10
2
2
2
V
C
G
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
G
2
2
2
G
1
1
1
1
1
1
1
1
1
1
1
1
1
G
1
1
1
1
V
C
50
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1
ABT32500–2
Widebus+, EPIC-
ΙΙ
B, and UBT are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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