
CardBus Socket Registers (Function 0)
126
September 2005
SCPS110
6
CardBus Socket Registers (Function 0)
The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report
and control socket-specific functions. The PCIxx12 controller provides the CardBus socket/ExCA base
address register (PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory
address space. Table 61 gives the location of the socket registers in relation to the CardBus socket/ExCA
base address.
In addition to the five required registers, the controller implements a register at offset 20h that provides power
management control for the socket.
16-Bit Legacy-Mode Base Address
CardBus Socket/ExCA Base Address
10h
44h
CardBus
Socket A
Registers
ExCA
Registers
Card A
20h
800h
844h
Host
Memory Space
address register’s base address.
Offsets are from the CardBus socket/ExCA base
00h
PCIxx12 Configuration Registers
Offset
Figure 61. Accessing CardBus Socket Registers Through PCI Memory
Table 61. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
00h
Socket mask
04h
Socket present state
08h
Socket force event
0Ch
Socket control
10h
Reserved
14h1Ch
Socket power management
20h
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.