參數(shù)資料
型號： SMK2-67025EV-45SB
廠商： TEMIC SEMICONDUCTORS
元件分類： Static RAM
英文描述： 8K X 16 DUAL-PORT SRAM, 45 ns, QFP84
封裝： MQFP-84
文件頁數(shù)： 9/23頁
文件大?。?/td> 355K
代理商： SMK2-67025EV-45SB
M67025E
Rev. G – July 6, 2000
17
AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
WRITE
PARAMETER
M
67025–30
M
67025–45
UNIT
CYCLE
PARAMETER
Min.
Max.
Min.
Max.
UNIT
BUSY TIMING (For Master 67025 only)
tBAA
BUSY Access time
to address
–
30
–
35
ns
tBDA
BUSY Disable time
to address
–
25
–
30
ns
tBAC
BUSY Access time
to Chip Select
–
25
–
30
ns
tBDC
BUSY Disable time
to Chip Select
–
20
–
25
ns
tWDD
Write Pulse to data Delay (1)
–
55
–
70
ns
tDDD
Write data valid to read data delay (1)
–
40
–
55
ns
tAPS
Arbitration priority set–up time (2)
5
–
5
–
ns
tBDD
BUSY disable to valid data
–
Note 3
–
Note 3
ns
BUSY TIMING (For Slave 67025 only)
tWB
Write to BUSY input (4)
0
–
0
–
ns
tWH
Write hold after BUSY (5)
20
–
25
–
ns
tWDD
Write pulse to data delay (6)
–
55
–
70
ns
tDDD
Write data valid to read data delay (6)
–
40
–
55
ns
Notes :
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For
Master 67025 only).
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) ot tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)”.
相關(guān)PDF資料
PDF描述
SMC9-65608EV-45SB 128K X 8 STANDARD SRAM, 45 ns, DIP32
SMDJ-65608EV-30SB 128K X 8 STANDARD SRAM, 30 ns, DFP32
SMDJ-65608EV-45SB 128K X 8 STANDARD SRAM, 45 ns, DFP32
SMK2-67025EV-30SB 8K X 16 DUAL-PORT SRAM, 30 ns, QFP84
SMFR-29C516E-31SB CMOS SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, TRUE OUTPUT, PQFP100
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