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SMJ320MCM41A
SINGLE SMJ320C40 MULTICHIP MODULE
SGMS719 – JUNE 1995
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
capacitance
Capacitance of a single ’C40 die is specified by design to be 15 pF max for both inputs and outputs. Module
networks add up to 5 pF. Characterization of die or substance capacitance is performed after any design
change. Power measurements taken for ’C40 die are made with an additional 80-pF load capacitance. Refer
to the SMJ320C40 data sheet for the test load circuit.
operational timings and module testing
Texas Instruments processing assures that operation is verified to published data sheet specifications on the
’C40 in die form. All voltage, timing, speed, and temperature specifications are met before any die is placed into
a multichip module. For this reason, it is unnecessary to verify all ’C40 voltage and timing parameters at the
module level.
Characterization of the ’MCM41A substrate shows that the module performs as an equivalent system of
discretely packaged ’C40 devices. This performance is assured through a full-frequency functional checkout
of the module that verifies selected worst-case timings. Refer to the SMJ320C40 data sheet for a complete
listing of timing diagrams and limits.
module test capability (future compatibility)
The ’C40 supports the IEEE-1149.1 testability standard, and all Test Access Port (TAP) pins are brought out
to the module footprint. This configuration allows users to test the module using Texas Instruments ASSET
tools or other boundary-scan control software. Proper software configuration allows users to debug or launch
code on the module via the ’C40 emulator and XDS pod. Both of these tools are used as part of outgoing module
testing.
The ’MCM41A supports the ASSET diagnostic family of products for verification and debug of boundary-scan
circuits, boards, and systems. For further information on ASSET, please contact your local TI sales
representative or authorized TI distributor.
A
ASSET is a trademark of Texas Instruments Incorporated.