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參數(shù)資料
| 型號(hào)： | SMJ320C6414DGADW60 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 64-BIT, 75 MHz, OTHER DSP, CPGA570 |
| 封裝： | 33 X 33 MM, CERAMIC, FCPGA-570 |
| 文件頁數(shù)： | 112/134頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | SMJ320C6414DGADW60 |
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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
79
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers
may be used to compensate any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 34 and Figure 15).
Figure 15 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 34. Board-Level Timings Example (see Figure 15)
NO.
DESCRIPTION
1
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
4
External device hold time requirement
5
External device setup time requirement
6
Control signal route delay
7
External device hold time
8
External device access time
9
DSP hold time requirement
10
DSP setup time requirement
11
Data route delay
1
2
3
4
5
6
7
8
10
11
ECLKOUTx
(Output from DSP)
ECLKOUTx
(Input to External Device)
Control Signals
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals
(Output from External Device)
Data Signals
(Input to DSP)
9
Control signals include data for Writes.
Data signals are generated during Reads from an external device.
Figure 15. Board-Level Input/Output Timings
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SM320C6414DGADW60 | 64-BIT, 75 MHz, OTHER DSP, CPGA570 |
| SM320C6416DGADW60 | 64-BIT, 75 MHz, OTHER DSP, CPGA570 |
| SMJ320C6701GLPW16 | 32-BIT, 166.66 MHz, OTHER DSP, CBGA429 |
| SMJ34010-50FDM | GRAPHICS PROCESSOR, CQCC68 |
| SMJ34010-40GBM | GRAPHICS PROCESSOR, CPGA68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C6415 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| SMJ320C6415C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| SMJ320C6415D | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| SMJ320C6415DGADW60 | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:TISSMJ320C6415DGADW60 MIL SPEC FIXED DSP |
| SMJ320C6416 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
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