參數(shù)資料
型號(hào): SM8580
廠商: Seiko NPC Corporation
元件分類: 溫度/濕度傳感器
英文描述: Real-time Clock IC with 4-bit Interface and Built-in Temperature Sensor
中文描述: 實(shí)時(shí)時(shí)鐘集成電路溫度傳感器與4位接口和內(nèi)置
文件頁(yè)數(shù): 16/23頁(yè)
文件大?。?/td> 179K
代理商: SM8580
SM8580AM
NIPPON PRECISION CIRCUITS—16
Timer Registers (Bank 2, Registers 4 to 8, E)
Timer control registers (registers 8, E)
I
TE bit (timer enable)
Timer countdown stop/start control bit.
When set to 1, the timer starts counting down.
When set to 0 during countdown, the timer stops.
I
TF bit (timer flag)
The timer flag is set to 1 when the timer counter
counts down to zero, occurring a timer event. It is
held at 1 until 0 is written to this bit. A 1 cannot be
written to TF.
I
TIE bit (timer interrupt enable)
This bit enables the timer interrupt output on
TIRQN when a timer event is occurred. If the TIE
is not set to 1, then no output occurs even if the TF
bit is set to 1. The TIRQN output is high imped-
ance when TIE is set to 0.
I
TI/TP bit (level/periodic interrupt mode select bit)
Sets the timer interrupt signal output mode.
The SM8580AM supports two timer function
modes.
TI/TP = 0 (level interrupt mode)
When a timer interrupt is occurred, TIRQN
goes LOW (if TIE = 1) and TF is set to 1.
TIRQN remains LOW and TF is held at 1 until
a 0 is written to the TF bit.
The timer operates by counting down until the
data is zero, then the TE bit is cleared and the
count stops automatically. However, if the timer
is started when the TF bit is 1, then the TE bit is
not cleared. The timer count register contents
remain zero after the count down stops.
TI/TP = 1 (periodic interrupt mode)
When a timer interrupt is occurred, TIRQN
goes LOW (if TIE = 1) and TF is set to 1.
TIRQN subsequently goes high impedance
after a fixed interval, but TF is held at 1 until a 0
is written to the TF bit.
The timer operates by counting down until the
data is zero, then the timer register data is
reloaded automatically after a fixed interval,
and the countdown restarts. This mode can be
used as a repetitive interval timer.
Timer source clock set register (register 8)
I
The register 8 bits 0 and 1 set the timer source
clock to one of four frequencies listed in the fol-
lowing table.
Bank
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
2
8
Timer setting
TE
TI/TP
E
Timer control
TF
TIE
Bank
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
2
8
Timer setting
TD1
TD0
TD1
TD0
Timer source clock
0
0
4096Hz
0
1
64Hz
1
0
1Hz
1
1
1/60Hz (1 minute)
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