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SM8580AM
NIPPON PRECISION CIRCUITS—11
FUNCTIONAL DESCRIPTION
Register Tables
Bank 0 (clock, calendar registers)
Bank 1 (alarm, FOUT registers)
Bank 2 (digital correction, timer registers)
I
All bits in register F and bits 2 to 3 in register E
are common to all register banks.
I
When alarm interrupts are not used, registers 0 to
8 in bank 1 can be used as RAM (total 36 bits).
I
When timer interrupts are not used, registers 4 to 5
in bank 2 can be used as RAM (total 8 bits).
I
When digital correction is not used, registers 0 to
1 in bank 2 can be used as RAM, excluding bit 3
(DT_ON) in register 1 (total 7 bits).
I
The BUSY/ADJ bit function is BUSY when read-
ing, and ADJ when writing.
I
The BUSY flag is set to 1 an interval of 244μs
before clock counter update timing.
I
Registers 6 and 7 in bank 2 are read-only registers,
and cannot be written to.
I
When power is applied, all register bits are unde-
fined, with the exception of bits FOS, TEST and
TEMP. Accordingly, these bits need to be initial-
ized. TEST and TEMP are automatically reset to 0
and FOS is automatically reset to 1 when power is
applied.
I
Bits marked # are all read-only bits fixed to 0.
These bits cannot be written to.
I
Bits marked * can be used as RAM bits.
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
0
Second registers
8
4
2
1
1
FOS
40
20
10
2
Minute registers
8
4
2
1
3
#
40
20
10
4
Hour registers
8
4
2
1
5
#
#
20
10
6
Day of week
register
#
4
2
1
7
Date registers
8
4
2
1
8
#
#
20
10
9
Month registers
8
4
2
1
A
#
#
#
10
B
Year registers
8
4
2
1
C
80
40
20
10
D
800
400
200
100
E
TEST
TEMP
2000
1000
F
Control register
Bank
SEL1
Bank
SEL0
STOP
BUSY/
ADJ
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
0
Second registers
8
4
2
1
1
AE
40
20
10
2
Minute registers
8
4
2
1
3
AE
40
20
10
4
Hour registers
8
4
2
1
5
AE
*
20
10
6
Day of week
register
AE
4
2
1
7
Date registers
8
4
2
1
8
AE
*
20
10
9
–
*
*
*
*
A
–
*
*
*
*
B
CE1 control
CTEMP CDT_ON
*
*
C
FOUT divider set
register
#
FD2
FD1
FD0
D
FOUT frequency
set register
FE
#
FD4
FD3
E
Alarm control
TEST
TEMP
AF
AIE
F
Control register
Bank
SEL1
Bank
SEL0
STOP
BUSY/
ADJ
Address
Register
Bit 3
Bit 2
Bit 1
Bit 0
0
Digital correction
registers
DT3
DT2
DT1
DT0
1
DT_ON
DT6
DT5
DT4
2
–
#
#
#
#
3
–
#
#
#
#
4
Timer counter set
registers
8
4
2
1
5
128
64
32
16
6
Timer counter
output registers
8
4
2
1
7
128
64
32
16
8
Timer setting
TE
TI/TP
TD1
TD0
9
–
#
#
#
#
A
–
#
#
#
#
B
–
*
*
*
*
C
–
*
*
*
*
D
–
*
*
*
*
E
Timer control
TEST
TEMP
TF
TIE
F
Control register
Bank
SEL1
Bank
SEL0
STOP
BUSY/
ADJ