
SMSC DS – SLC90E66
Page 6
Rev. 07/10/2002
4.1.25
4.1.26
4.1.27
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
SBMISCH South Bridge Miscellaneous High Register (Function 0).....................................................64
SHUTSC - Shutdown Special Cycle Code Register (Function 0).........................................................65
SGSC - Stop Grant Special Cycle Code Register (Function 0)............................................................65
PCI
TO
ISA/EIO
B
RIDGE
I/O
R
EGISTERS
..........................................................................................................65
DMA Registers.....................................................................................................................................65
Interrupt Controller Registers (I/O).......................................................................................................71
Counter/Timer Registers ......................................................................................................................76
NMI Registers (I/O) ..............................................................................................................................79
Real Time Clock Registers...................................................................................................................80
Advanced Power Management (APM) Registers (I/O)........................................................................81
X-Bus, Coprocessor, and Reset Registers...........................................................................................82
5.0
IDE CONTROLLER REGISTER DESCRIPTION.............................................................................................84
5.1
IDE
C
ONTROLLER
PCI
R
EGISTER
D
ESCRIPTION
(F
UNCTION
1) ...........................................................................84
5.1.1
VID - Vendor Identification Register (Function 1).................................................................................84
5.1.2
DID - Device Identification Register (Function 1)..................................................................................84
5.1.3
PCICMD - PCI Command Register (Function 1)..................................................................................84
5.1.4
PCISTS - PCI Device Status Register (Function 1)..............................................................................85
5.1.5
RID - Revision Identification Register (Function 1)...............................................................................85
5.1.6
CLASSCODE - Class Code Register (Function 1)...............................................................................85
5.1.7
MLT - Master Latency Timer Register (Function 1)..............................................................................86
5.1.8
HEDT - Header Type Register (Function 1) .........................................................................................86
5.1.9
IDEBASE1 - PCI Base Address Register 1 (Function 1)......................................................................86
5.1.10
IDEBASE2 - PCI Base Address Register 2 (Function 1)......................................................................87
5.1.11
IDEBASE3 - PCI Base Address Register 3 (Function 1)......................................................................87
5.1.12
IDEBASE4 - PCI Base Address Register 4 (Function 1)......................................................................87
5.1.13
BMIBA - Bus Master Interface Base Address Register (Function 1) ....................................................88
5.1.14
SVID - Subsystem Vendor ID (Function 1)...........................................................................................88
5.1.15
SID - Subsystem ID (Function 1)..........................................................................................................88
5.1.16
INTLINE - PCI IDE Interrupt Line (Function 1) .....................................................................................89
5.1.17
INTPIN - PCI IDE Interrupt Pin (Function 1).........................................................................................89
5.1.18
IDETIM - Primary/Secondary IDE Timing Registers (Function 1).........................................................89
5.1.19
SIDETIM - Slave IDE Timing Register (Function 1)..............................................................................91
5.1.20
IDESRC - IDE Slew Rate Control Register (Function 1) ......................................................................92
5.1.21
IDESTATUS - IDE Status Register (Function 1)...................................................................................92
5.1.22
UDMACTL - Ultra DMA Control Register (Function 1) .........................................................................92
5.1.23
UDMATIM - Ultra ATA/66 Timing Register (Function 1).......................................................................93
5.1.24
SMSC TEST - SMSC Test Register.....................................................................................................94
5.2
IDE
C
ONTROLLER
I/O
R
EGISTERS
....................................................................................................................95
5.2.1
BMICx - Bus Master IDE Command Register Primary/Secondary (I/O))..............................................95
5.2.2
BMISx - Bus Master IDE Status Register (I/O).....................................................................................96
5.2.3
BMIDTPx - Bus Master IDE Descriptor Table Pointer Register (I/O)....................................................97
6.0
USB REGISTER DESCRIPTION.....................................................................................................................98
6.1
USB
H
OST
C
ONTROLLER
PCI
C
ONFIGURATION
R
EGISTERS
(F
UNCTION
2)...........................................................98
6.1.1
VID - Vendor ID Register (Function 2)..................................................................................................98
6.1.2
DID - Device ID Register (Function 2)..................................................................................................98
6.1.3
PCICMD - PCI Command Register (Function 2)..................................................................................98
6.1.4
PCISTS - Status Register (Function 2).................................................................................................99
6.1.5
RID - Revision ID Register (Function 2) ............................................................................................100
6.1.6
CLASSCODE - Class Code Register (Function 2).............................................................................100
6.1.7
CLS - Cache Line Size (Function 2)...................................................................................................100
6.1.8
LTR - Latency Timer (Function 2)......................................................................................................100
6.1.9
HTR - Header Type Register (Function 2)..........................................................................................101
6.1.10
BIST...................................................................................................................................................101
6.1.11
BAR - Base Address Register 0 (Function 2).....................................................................................101
6.1.12
SVID - Subsystem Vendor ID Register...............................................................................................101
6.1.13
SID - Subsystem ID Register .............................................................................................................102
6.1.14
ILR - Interrupt Line Register (Function 2)...........................................................................................102
6.1.15
IPR - Interrupt Pin Register (Function 2) ............................................................................................102
6.1.16
MGR - Min_Gnt Register (Function 2)................................................................................................102
6.1.17
MLR - Max_Lat. Register (Function 2) ...............................................................................................103
6.1.18
TME - Test Mode Enable Register.....................................................................................................103
6.1.19
OME - ASIC Operational Mode Enable Register................................................................................104
6.2
O
PEN
H
OST
C
ONTROLLER
I
NTERFACE
M
EMORY
M
APPED
R
EGISTERS
................................................................104