參數(shù)資料
型號(hào)： SLC90E66-UF
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 外設(shè)及接口
英文描述： Victory66 Enhanced PCI South Bridge with Ultra ATA/66 IDE Controller
中文描述： MULTIFUNCTION PERIPHERAL, PBGA324
封裝： PLASTIC, BGA-324
文件頁(yè)數(shù)： 9/257頁(yè)
文件大?。?/td> 1333K
代理商： SLC90E66-UF
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SMSC DS – SLC90E66
Page 9
Rev. 07/10/2002
8.7
S
ERIAL
I
NTERRUPTS
(SIRQ)..........................................................................................................................171
8.7.1
SIRQ Protocol ....................................................................................................................................171
8.8
T
IMER
/C
OUNTERS
.........................................................................................................................................173
8.8.1
Counter 0 ...........................................................................................................................................173
8.8.2
Counter 1 ...........................................................................................................................................173
8.8.3
Counter 2 ...........................................................................................................................................173
8.8.4
The Interval Timer Programming Interface.........................................................................................173
8.9
R
EAL
T
IME
C
LOCK
M
ODULE
...........................................................................................................................175
8.9.1
RTC Registers and RAM....................................................................................................................175
8.9.2
Control Register A..............................................................................................................................177
8.9.3
Control Register B..............................................................................................................................178
8.9.4
Control Register C..............................................................................................................................179
8.9.5
Register D ..........................................................................................................................................179
8.9.6
RTC Update Cycle .............................................................................................................................179
8.9.7
RTC Interrupt .....................................................................................................................................180
8.9.8
Lockable RAM Ranges.......................................................................................................................180
8.9.9
RTC External Connections.................................................................................................................180
8.10
XB
US
S
UPPORT
............................................................................................................................................180
8.11
S
TAND
A
LONE
I/O
APIC
S
UPPORT
................................................................................................................180
8.12
S
YSTEM
R
ESET
L
OGIC
...................................................................................................................................181
8.13
H
OST
I
NTERFACE
L
OGIC
................................................................................................................................181
9.0
USB HOST CONTROLLER FUNCTIONAL OVERVIEW ..............................................................................182
9.1
H
OST
C
ONTROLLER
D
RIVER
...........................................................................................................................182
9.1.1
Bandwidth Allocation..........................................................................................................................183
9.1.2
List Management................................................................................................................................183
9.2
H
OST
C
ONTROLLER
......................................................................................................................................183
9.2.1
USB States.........................................................................................................................................183
9.2.2
Frame Management...........................................................................................................................183
9.2.3
List Processing...................................................................................................................................183
9.2.4
USB Power Management Functions ..................................................................................................184
10.0
IDE CONTROLLER FUNCTIONAL OVERVIEW...........................................................................................186
10.1
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.2
10.3.3
10.4
10.4.1
10.4.2
10.5
10.5.1
10.5.2
10.6
IDE
C
ONFIGURATIONS
...................................................................................................................................186
IDE
R
EGISTER
B
LOCKS
.................................................................................................................................186
Legacy Mode......................................................................................................................................186
PCI Native Mode................................................................................................................................187
PIO
IDE
O
PERATIONS
...................................................................................................................................187
PIO IDE Data Transfer Cycle .............................................................................................................188
32-Bit PIO IDE Data Transfer Cycle...................................................................................................188
PIO IDE Data Prefetching and Posting...............................................................................................188
B
US
M
ASTER
O
PERATIONS
............................................................................................................................189
Physical Region Descriptor (PRD) .....................................................................................................189
Bus Master Transfer Operation..........................................................................................................189
U
LTRA
ATA/66
S
YNCHRONOUS
DMA
O
PERATION
...........................................................................................190
Ultra ATA/66 Signals..........................................................................................................................190
Ultra ATA/66 Operation......................................................................................................................191
IDE
D
ATA
B
UFFER
........................................................................................................................................192
11.0
POWER MANAGEMENT FUNCTIONAL OVERVIEW..................................................................................193
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
11.3.1
11.3.2
11.3.3
11.3.4
S
YSTEM
C
LOCK
C
ONTROL
.............................................................................................................................194
Host Clock Control .............................................................................................................................196
Stop Clock State Example Sequence.................................................................................................200
PCI Clock Control...............................................................................................................................202
P
ERIPHERAL
D
EVICE
M
ANAGEMENT
................................................................................................................203
Device Monitor and Idle Timer............................................................................................................203
Device Trap........................................................................................................................................204
Peripheral Device Management.........................................................................................................204
PCI/ISA Peripheral Devices ...............................................................................................................204
Device Specific Details.......................................................................................................................206
S
USPEND
/R
ESUME
C
ONTROL
M
ECHANISM
......................................................................................................221
Suspend Modes .................................................................................................................................221
System Resume Mechanism..............................................................................................................222
Suspend and Resume Control Signaling............................................................................................223
Alternate AT Register Access Mode (Shadow Registers) ..................................................................240
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