
SMSC DS – SLC90E66
Page 8
Rev. 07/10/2002
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.3.15
7.3.16
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
PMSTS - Power Management Status Register (I/O)..........................................................................136
PMEN - Power Management Resume Enable Register (I/O).............................................................137
PMCNTRL - Power Management Control Register (I/O)...................................................................137
PMTMR - Power Management Timer Register (I/O) ..........................................................................138
GPSTS - General Purpose Status Register (I/O) ..............................................................................139
GPEN - General Purpose Enable Register (I/O) ................................................................................140
PCNTRL - Processor Control Register (I/O)......................................................................................140
PLVL2 - Processor Level 2 Register (I/O) .........................................................................................141
PLVL3 - Processor Level 3 Register (I/O) .........................................................................................142
GLBSTS - Global Status Register (I/O)..............................................................................................142
DEVSTS - Device Status Register (I/O).............................................................................................143
GLBEN - Global Enable Register (I/O)...............................................................................................144
GLBCTL - Global Control Register (I/O).............................................................................................145
DEVCTL - Device Control Register (I/O)...........................................................................................146
GPIREG - General Purpose Input Register (I/O)................................................................................148
GPOREG - General Purpose Output Register (I/O)...........................................................................148
SMB
US
I/O
R
EGISTERS
.................................................................................................................................149
SMBHSTSTS - SMBus Host Status Register (I/O).............................................................................149
SMBSLVSTS - SMBus Slave Status Register (I/O)............................................................................150
SMBHSTCNT - SMBus Host Control Register (I/O)..........................................................................151
SMBHSTCMD - SMBus Host Command Register (I/O)....................................................................151
SMBHSTADD - SMBus Host Address Register (I/O).........................................................................152
SMBHSTDAT0 - SMBus Host Data 0 Register (I/O).........................................................................152
SMBHSTDAT1 - SMBus Host Data 1 Register (I/O).........................................................................152
SMBBLKDAT - SMBus Block Data Register (I/O).............................................................................153
SMBSLVCNT - SMBus Slave Control Register (I/O).........................................................................153
SMBSHDWCMD - SMBus Shadow Command Register (I/O)...........................................................154
SMBSLVEVT - SMBus Slave Event Register (I/O).............................................................................154
SMBSLVEVT - SMBus Slave Data Register (I/O).............................................................................154
8.0
PCI/ISA BRIDGE FUNCTIONAL OVERVIEW...............................................................................................155
8.1
M
EMORY AND
IO
A
DDRESS
M
AP
.....................................................................................................................155
8.1.1
I/O Accesses......................................................................................................................................155
8.1.2
Memory Access..................................................................................................................................155
8.1.3
BIOS Memory Space..........................................................................................................................155
8.2
PCI
I
NTERFACE
............................................................................................................................................157
8.2.1
PCI Transaction Termination..............................................................................................................157
8.2.2
PCI Bus Arbitration.............................................................................................................................158
8.2.3
PCI Parity...........................................................................................................................................158
8.3
ISA/EIO
I
NTERFACE
.....................................................................................................................................158
8.4
DMA
C
ONTROLLER
.......................................................................................................................................158
8.4.1
DMA Transfer Modes .........................................................................................................................159
8.4.2
DMA Transfer Types..........................................................................................................................159
8.4.3
DMA Timing .......................................................................................................................................160
8.4.4
DMA Buffer.........................................................................................................................................160
8.4.5
DREQ and nDACK Latency Control...................................................................................................160
8.4.6
DMA Channel Priority.........................................................................................................................160
8.4.7
Address Compatibility Mode...............................................................................................................161
8.4.8
DMA Transfer Sizes...........................................................................................................................161
8.4.9
Address Shifting in 16-Bit DMA I/O Transfer......................................................................................161
8.4.10
Auto initialization ................................................................................................................................161
8.4.11
Special DMA Software Commands....................................................................................................161
8.4.12
ISA Refresh........................................................................................................................................162
8.5
PCI
DMA ....................................................................................................................................................162
8.5.1
PC/PCI DMA ......................................................................................................................................162
8.5.2
Distributed DMA (DDMA) ..................................................................................................................165
8.6
I
NTERRUPT
C
ONTROLLER
...............................................................................................................................167
8.6.1
Programming the Interrupt Controller.................................................................................................167
8.6.2
End of Interrupt Operation..................................................................................................................168
8.6.3
Modes of Operation............................................................................................................................169
8.6.4
Cascade Mode...................................................................................................................................170
8.6.5
Edge and Level Triggered Mode........................................................................................................170
8.6.6
Interrupt Masks...................................................................................................................................170
8.6.7
Interrupt Controller Status ..................................................................................................................171
8.6.8
Interrupt Steering................................................................................................................................171