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參數(shù)資料
| 型號： | SLC88B17QFP |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 50/54頁 |
| 文件大?。?/td> | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 54
Rev. 09/20/99
SLC88B17 REVISIONS
PAGE(S)
SECTION/FIGURE/ENTRY
CORRECTION
DATE
REVISED
1, 5, 12
Positive Decoding Memory
Range
The fixed memory range for positive decode will be
changed in the data sheet from (FFFF0000h -
FFFFFFFFh) to (0FFF0000h - 0FFFFFFFh).
9/20/99
5
FIGURE 3
nC/BE[3:0] changed to C/nBE[3:0]
9/20/99
5
PCI to ISA Bridge
When configured for positive decoding, the
SLC88B17 does not subtractive decode.
9/20/99
6
Pin Configuration
pin n0WS changed to nZEROWS
9/20/99
15
Vendor ID
The VID register of the SLC88B17 reads 10B8h
instead of 1055h, as stated in the data sheet. The
default value of the VID register will be changed from
1055h to 10B8h in the data sheet.
9/20/99
16
Class Code Register
Register mnemonic CLASSC changed to
CLASSCODE
9/20/99
17
SYSCLK Divide by 3
The SYSCLK Divider Select feature controlled by bit
7 of the ISA I/O Recovery Timer Register
(Configuration space, offset 40h). Function of bit 7 =
1 will be changed from “Divide PCI clock by 3” to
“Reserved.”
9/20/99
17
Delay Transaction
Delay transaction (Configuration register 41h, bit 6) is
always disabled. The bit will be changed to reserved
and all references made to the delay transaction will
be removed.
9/20/99
17
Dynamic RAM Slow
Refresh Rate
The function of AT DRAM Slow Refresh bit (bit 1 of
Miscellaneous Control Register, configuration space,
offset 41h) will be changed from “DRAM refresh rate
is extended to 60us” to “refresh rate is extended to
208us.”
9/20/99
17
8 Bit I/O Recovery Time
The ISA I/O Recovery Timer Register (Configuration
space, Offset 40h) is used to add additional recovery
delay between PCI initiated 16 bit and 8 bit I/O cycles
to the ISA bus. Bit [5:3] are used to program
additional SYSCLK cycles to the 8 bit I/O recovery
time in addition to the minimum delay of 3.5
SYSCLKs. The function of Bit [5:3] = 101 will be
changed from “adding 5 additional SYSCLKs” to
“adding 4 additional SYSCLKs.” And the function of
Bit [5:3] = 000 will be added as “8 additional
SYSCLKs.”
9/20/99
27 – 52
Electrical Characteristics
NEW SECTION
9/20/99
29
IRQSER Sampling Periods
IOCHK changed to nIOCHK
9/20/99
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