參數(shù)資料
型號(hào)： SLC88B17QFP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 總線控制器
英文描述： ISA BUS CONTROLLER, PQFP160
封裝： QFP-160
文件頁(yè)數(shù)： 2/54頁(yè)
文件大?。?/td> 333K
代理商： SLC88B17QFP
SMSC DS – SLC88B17
Page 10
Rev. 09/28/99
NAME
TYPE
DESCRIPTION
LA[23-17]
I/O
ISA LA[23-17]. LA[23-17] address lines allow accesses to physical memory on the
ISA bus up to 16 Mbytes. They are outputs when the SLC88B17 owns the ISA bus.
They become inputs whenever an ISA master owns the ISA bus. These signals are
at an undefined state upon nPCIRST.
During Reset: High-Z
After Reset: Undefined.
SD[15-0]
I/O
System Data.
16-bit data path for devices residing on the ISA bus. They are
undefined during refresh.
During Reset: High-Z
After Reset: Undefined.
nSMEMR
O
Standard Memory Read. The SLC88B17 asserts nSMEMR to request an ISA
memory slave to drive data onto the data lines. If the memory access is below the
1Mbyte range during DMA, SLC88B17 master, or ISA master cycles, the SLC88B17
asserts nSMEMR. nSMEMR is a delayed version of nMEMR.
During Reset: High-Z
After Reset: High
nSMEMW
O
Standard Memory Write. The SLC88B17 asserts nSMEMR to request an ISA
memory slave to receive data from the data lines. If the memory access is below the
1Mbyte range during DMA, SLC88B17 master, or ISA master cycles, the SLC88B17
asserts nSMEMW. nSMEMW is a delayed version of nMEMW.
During Reset: High-Z
After Reset: High
nMEMR
I/O
Memory Read. nMEMR is the command to a memory slave that it may drive data
onto the ISA data bus. nMEMR is an output when the SLC88B17 owns the ISA bus
or during refresh cycles. nMEMR is an input when an ISA master owns the ISA bus.
For DMA cycles, the SLC88B17, as a master, asserts nMEMR.
During Reset: High-Z After Reset: High.
nMEMW
I/O
Memory Write. nMEMW is the command to a memory slave that it may latch data
from the ISA data bus. nMEMW is an output when the SLC88B17 owns the ISA bus.
nMEMW is an input when an ISA master owns the ISA bus. For DMA cycles, the
SLC88B17, as a master, asserts nMEMW.
During Reset: High-Z
After Reset: High
AEN
O
Address Enable. AEN is asserted during DMA cycles to prevent I/O slaves from
claiming DMA cycles as valid I/O cycles. When de-asserted, it indicates that an I/O
slave may respond to the bus command. When asserted, it informs I/O slave that a
DMA transfer is occurring on the ISA bus.
The signal is driven high during SLC88B17 initiated refresh cycles, it is driven low
upon nPCIRST.
During Reset: High-Z
After Reset: Low
BALE
O
Address Latch Enable. BALE is asserted by the SLC88B17 to indicate that the
address and nSBHE signal lines are valid. The LA[23-17] are latched on the trailing
edge of BALE. BALE remains asserted throughout DMA and ISA master cycles.
During Reset: High-Z
After Reset: Low
nSBHE
I/O
System Byte High Enable. When asserted indicates that a byte is being
transferred on the SD[15-8] of the data bus. It is negated during refresh cycle.
nSBHE is an output when the SLC88B17 owns the ISA bus. It becomes an input
when an external ISA master owns the ISA bus.
During Reset: High-Z
After Rest: Undefined
nIOCHK
I
IO Channel Check. When asserted, the signal indicates that a parity or an
uncorrectable error has occurred for a device or memory on the ISA bus.
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