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參數(shù)資料
| 型號： | SKY72310-362 |
| 廠商： | Skyworks Solutions Inc |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER 2.1GHZ 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 分?jǐn)?shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘，晶體 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.1GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -45°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 863-1272-6 |
DATA SHEET SKY72310 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
10
July 30, 2008 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 200705E
S1064
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
01
XX
Reference Frequency Divider Index
Figure 8. Reference Frequency Dividers Register (Write Only)
S1065
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
01
10
Phase Detector Gain
Power Steering/Lock Detect Enable
Figure 9. Phase Detector/Charge Pump Control Register (Write Only)
S1066
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
01
11
X
MSB
LSB
Full Power Down
Synthesizer Power Down
Synthesizer Mode
Synthesizer
ΔΣ Fractionality
Multiplexer Output Selection
Mux_out Pin Three-State Enable
Figure 10. Power Down/Multiplexer Output Select Control Register (Write Only)
The Phase Detector/Charge Pump Control Register allows control
of the gain for the phase detector and configuration of the
LD/PSmain signal (pin 4) for frequency power steering or lock
detection. As shown in Figure 9, the values to be loaded are:
Phase Detector Gain = Five-bit value for programmable phase
detector gain. Range is from 0 to 31 decimal for 31.25 to 1000
A/ 2π radian, respectively.
Power Steering Enable = One-bit flag to enable the frequency
power steering circuitry of the phase detector. When this bit is
cleared, the LD/PSmain pin is configured to be a lock detect,
active low, open collector pin. When this bit is set, the
LD/PSmain pin is configured to be a frequency power steering
pin and can be used to bypass the external loop filter to provide
faster frequency acquisition.
The Power Down/Multiplexer Output Select Control Register
allows control of the power-down modes, internal multiplexer
output, and
Σ synthesizer fractionality. As shown in Figure 10,
the values to be loaded are:
Full Power Down = One-bit flag to power down the SKY72310
except for the reference oscillator and the serial interface. When
this bit is cleared, the SKY72310 is powered up. When this bit is
set, the SKY72310 is in full power-down mode excluding the
Mux_out signal (pin 24).
Synthesizer Power Down = One-bit flag to power down the
synthesizer. When this bit is cleared, the synthesizer is powered
up. When this bit is set, the synthesizer is in power-down mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SKY72310-362LF | 功能描述:IC SYNTHESIZER 2.1GHZ 24-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| SKY72310-362LF_EVB_NON SKYWORKS VCO | 制造商:Skyworks Solutions Inc 功能描述:Eval Kit for SKY72310-362LF TW14-D880, Bulk |
| SKY73001 | 制造商:SKYWORKS 制造商全稱:SKYWORKS 功能描述:2 - 3500 MHz Direct Conversion Mixer |
| SKY73001_06 | 制造商:SKYWORKS 制造商全稱:SKYWORKS 功能描述:2 - 3500 MHz Direct Conversion Mixer |
| SKY73001-11 | 制造商:Skyworks Solutions Inc 功能描述:2 MHz - 3500 MHz RF/MICROWAVE DOUBLE BALANCED MIXER |
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