參數(shù)資料
型號: SKY72310-362
廠商: Skyworks Solutions Inc
文件頁數(shù): 14/19頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 2.1GHZ 24QFN
標準包裝: 1
類型: 分數(shù) N 合成器(RF)
PLL:
輸入: 時鐘,晶體
輸出: 時鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -45°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 標準包裝
其它名稱: 863-1272-6
DATA SHEET SKY72310 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
4
July 30, 2008 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 200705E
LSB last while the CS signal is low. If the CS signal is low for
more than 16 clock cycles, only the last address or data bits are
used to load the registers.
Register Programming
Register programming equations, described in this section, use
the following variables and constants:
Nfractional
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (Fref) multiplying factor so that the
resulting frequency is equal to the desired VCO
frequency.
Ninteger
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (Fref) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
Nreg
Nine-bit unsigned input value to the divider ranging
from 0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
divider
This constant equals 262144 when the
Σ modulator
is in 18-bit mode, and 1024 when the
Σ modulator is
in 10-bit mode.
dividend
When in 18-bit mode, this is the 18-bit signed input
value to the
Σ modulator, ranging from –131072 to
+131071 and providing 262144 steps, each step equal
to Fdiv_ref/218 Hz.
When in 10-bit mode, this is the 10-bit signed input
value to the
Σ modulator, ranging from –512 to +511
and providing 1024 steps, each step equal to
Fdiv_ref/210
Hz.
FVCO
Desired VCO frequency.
Fdiv_ref
Divided reference frequency presented to the phase
detector.
Fractional-N Applications. The desired division ratio for the
synthesizer is given by:
ref
_
div
VCO
fractional
F
N
=
where Nfractional must be between 37.5 and 537.5.
The value to be programmed in the Divider Register is given by:
32
)
N
(
Round
N
fractional
reg
=
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for Nreg are from 6 to 505
inclusive.
The value to be programmed by either of the Dividend Registers
(MSB or LSB) is given by:
)]
32
N
(
divider
[
Round
dividend
reg
fractional
×
=
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
NOTE: Because of the high fractionality of the SKY72310, there is
no practical need for any integer relationship between the
reference frequency and the channel spacing or desired
VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
X
A3
A2
A1
A0
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
Clock
Last
Data
CS
C1413
Figure 3. Serial Transfer Timing Diagram
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