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參數(shù)資料
| 型號： | SKY72300-362 |
| 廠商： | Skyworks Solutions Inc |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER 2.1GHZ 24QFN |
| 產(chǎn)品目錄繪圖： | 24-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 分?jǐn)?shù) N 合成器 |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘，晶體 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.1GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 587 (CN2011-ZH PDF) |
| 其它名稱： | 863-1077-6 |
DATA SHEET SKY72300-362 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
8
July 30, 2007 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 200731B
Case 1: To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum
divide ratio is 32, the reference frequency (Fdiv_ref) must be a maximum of 12.5 MHz. Choosing a reference
frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore:
Ninteger
=
Fvco_aux
Fdiv_ref
=
400
8
=
50
The value to be programmed in the Auxiliary Divider Register is:
Nreg = Ninteger – 32
= 50 – 32
= 18 (decimal)
= 000010010 (binary)
Summary:
Auxiliary Divide Register = 0 0001 0010
C1416
Figure 5. Integer-N Applications: Sample Calculation
For the auxiliary synthesizer, the Auxiliary Dividend Register holds
the 10 bits of the dividend. The registers that control the auxiliary
synthesizer’s divide ratio are to be loaded in the following order:
Auxiliary Divider Register
Auxiliary Dividend Register (at which point the new divide ratio
takes effect)
NOTE: When in integer mode, the new divide ratios take effect as
soon as the Main or Auxiliary Divider Register is loaded.
Direct Digital Modulation
The high fractionality and small step size of the SKY72300-362
allow the user to tune to practically any frequency in the VCO’s
operating range. This allows direct digital modulation by
programming the different desired frequencies at precise instants.
Typically, the channel frequency is programmed by the Main
Divider and MSB/LSB Dividend Registers, and the instantaneous
frequency offset from the carrier is programmed by the
Modulation Data Register.
The Modulation Data Register can be accessed in three ways as
defined in the following subsections.
Normal Register Write. A normal 16-bit serial interface write
occurs when the CS signal is 16 clock cycles wide. The
corresponding 16-bit modulation data is simultaneously
presented to the Data pin. The content of the Modulation Data
Register is passed to the modulation unit at the next falling edge
of the divided main VCO frequency (Fpd_main).
Short CS Through Data Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented to the Data pin. The Data
pin is the default pin used to enter modulation data directly in the
Modulation Data Register with shortened CS strobes.
This method of data entry eliminates the register address
overhead on the serial interface. All serial interface bits are re-
synchronized internally at the reference oscillator frequency. The
content of the Modulation Data Register is passed to the
modulation unit at the next falling edge of the divided main VCO
frequency (Fpd_main).
Short CS Through Mod_in Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented on the Mod_in pin, an
alternate pin used to enter modulation data directly into the
Modulation Data Register with shortened CS strobes. This mode is
selected through the Modulation Control Register.
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| SKY72301-22 | 功能描述:鎖相環(huán) - PLL 1GHz / 500MHz Syn. Phase noise-96dBc/Hz RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SKY72302 | 制造商:SKYWORKS 制造商全稱:SKYWORKS 功能描述:Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer |
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| SKY72310-362 | 功能描述:IC SYNTHESIZER 2.1GHZ 24QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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