參數(shù)資料
型號: SKY72300-362
廠商: Skyworks Solutions Inc
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 2.1GHZ 24QFN
產(chǎn)品目錄繪圖: 24-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 分?jǐn)?shù) N 合成器
PLL:
輸入: 時鐘,晶體
輸出: 時鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 587 (CN2011-ZH PDF)
其它名稱: 863-1077-6
DATA SHEET SKY72300-362 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
200731B Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 30, 2007
5
X
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
Clock
Last
Data
CS
C1413
Figure 3. Serial Transfer Timing Diagram
FVCO
Desired VCO frequency (either Fvco_main or Fvco_aux).
Fdiv_ref
Divided reference frequency presented to the phase
detector (either Fref_main or Fref_aux).
Fractional-N Applications. The desired division ratio for the
main and auxiliary synthesizers is given by:
ref
_
div
VCO
fractional
F
N
=
where Nfractional must be between 37.5 and 537.5.
The value to be programmed by the Main or Auxiliary Divider
Register is given by:
32
)
N
(
Round
N
fractional
reg
=
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for Nreg are from 6 to 505
inclusive.
The value to be programmed by either of the MSB/LSB Dividend
Registers or the Auxiliary Dividend Register is given by:
)]
32
N
(
divider
[
Round
dividend
reg
fractional
×
=
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
NOTE: Because of the high fractionality of the SKY72300-362,
there is no practical need for any integer relationship
between the reference frequency and the channel spacing
or desired VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
Integer-N Applications. The desired division ratio for the main or
auxiliary synthesizer is given by:
ref
_
div
main
_
vco
eger
int
F
N
=
where Ninteger is an integer number from 32 to 543.
The value to be programmed by the Main or Auxiliary Divider
Register is given by:
32
N
eger
int
reg
=
When in integer mode, allowed values for Nreg are from 0 to 511
for both the main and auxiliary synthesizers.
NOTE: As with all integer-N synthesizers, the minimum step size
is related to the crystal frequency and reference frequency
division ratio.
A sample calculation for an integer-N application is provided in
Figure 5.
Register Loading Order. In applications where the main
synthesizer is in 18-bit mode, the Main Dividend MSB Register
holds the 10 MSBs of the dividend and the Main Dividend LSB
Register holds the 8 LSBs of the dividend. The registers that
control the main synthesizer’s divide ratio are to be loaded in the
following order:
Main Divider Register
Main Dividend LSB Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
In applications where the main synthesizer is in 10-bit mode, the
Main Dividend MSB Register holds the 10 bits of the dividend. The
registers that control the main synthesizer’s divide ratio are to be
loaded in the following order:
Main Divider Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
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