參數(shù)資料
型號(hào)： SKY72300-21
廠商： Skyworks Solutions Inc
文件頁(yè)數(shù)： 22/22頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER 2.1GHZ 28-EPTSSOP
產(chǎn)品目錄繪圖： 28-TSSOP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 分?jǐn)?shù) N 合成器
PLL： 是
輸入： 時(shí)鐘，晶體
輸出： 時(shí)鐘，晶體
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.1GHz
除法器/乘法器： 是/無(wú)
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SOIC（0.173"，4.40mm 寬）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 28-TSSOP 裸露焊盤(pán)
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 587 (CN2011-ZH PDF)
其它名稱(chēng)： 863-1076-6
DATA SHEET SKY72300-21 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101217N Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 11, 2009
9
Table 1. SKY72300-21 Register Map
Address (Hex)
Register (Note 1)
Length (Bits)
Address (Bits)
0
Main Divider Register
12
4
1
Main Dividend MSB Register
12
4
2
Main Dividend LSB Register
12
4
3
Auxiliary Divider Register
12
4
Auxiliary Dividend Register
12
4
5
Reference Frequency Dividers Register
12
4
6
Phase Detector/Charge Pump Control Register
12
4
7
Power Down/Multiplexer Output Select Control Register
12
4
8
Modulation Control Register
12
4
9
—
Modulation Data Register
Modulation Data Register (Note 2) — direct input
12
2 ≤ length ≤ 12 bits
4
0
Note 1: All registers are write only.
Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
When the sum of the dividend and modulation data lie outside this
range, the value of Ninteger must be changed.
For a more detailed description of direct digital modulation
functionality, refer to the Skyworks Application Note, Direct Digital
Modulation Using the SKY72300-21, SKY72301, and SKY72302
Dual Synthesizers/PLLs (document number 101349).
Register Descriptions
Table 1 lists the 10 16-bit registers that are used to program the
SKY72300-21. All register writes are programmed address first,
followed directly with data. MSBs are entered first. On power up,
all registers are reset to 0x000 except registers at addresses 0x0
and 0x3, which are set to 0x006.
Main Synthesizer Registers
The Main Divider Register contains the integer portion closest to
the desired fractional-N (or the integer-N) value minus 32 for the
main synthesizer. This register, in conjunction with the Main
Dividend MSB and LSB Registers (which control the fraction offset
from –0.5 to +0.5), allows selection of a precise frequency. As
shown in Figure 6, the value to be loaded is:
Main Synthesizer Divider Index = Nine-bit value for the integer
portion of the main synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
The Main Dividend MSB and LSB Registers control the fraction
part of the desired fractional-N value and allow an offset of –0.5
to +0.5 to the main integer selected through the Main Divider
Register. As shown in Figures 7 and 8, values to be loaded are:
Main Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs
of the 18-bit dividend for the main synthesizer.
Main Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs
of the 18-bit dividend for the main synthesizer.
The Main Dividend Register MSB and LSB values are 2's
complement format.
NOTE: When in 10-bit mode, the Main Dividend LSB Register is
not required.
Auxiliary Synthesizer Registers
The Auxiliary Divider Register contains the integer portion closest
to the desired fractional-N (or integer-N) value minus 32 for the
auxiliary synthesizer. This register, in conjunction with the
Auxiliary Dividend Register (which controls the fraction offset from
–0.5 to +0.5), allows selection of a precise frequency. As shown
in Figure 9, the value to be loaded is:
Auxiliary Synthesizer Divider Index = Nine-bit value for the
integer portion of the auxiliary synthesizer dividers. Valid values
for this register are from 6 to 505 (fractional-N) or from 0 to 511
(integer-N).
The Auxiliary Dividend Register controls the fraction part of the
desired fractional-N value and allows an offset of –0.5 to +0.5 to
the auxiliary integer selected through the Auxiliary Divider
Register. As shown Figure 10, the value to be loaded is:
Auxiliary Synthesizer Dividend = Ten-bit value for the auxiliary
synthesizer dividend.
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SKY72300-362 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 2.1GHz 100Hz step Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SKY72301-22 功能描述:鎖相環(huán) - PLL 1GHz / 500MHz Syn. Phase noise-96dBc/Hz RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
SKY72302 制造商:SKYWORKS 制造商全稱(chēng):SKYWORKS 功能描述:Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer
SKY72302-21 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6.1GHz 400Hz step Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SKY72310-362 功能描述:IC SYNTHESIZER 2.1GHZ 24QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類(lèi)型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱(chēng):23S08-5HPGG
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