參數(shù)資料
型號(hào)： SKY72300-21
廠商： Skyworks Solutions Inc
文件頁(yè)數(shù)： 21/22頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER 2.1GHZ 28-EPTSSOP
產(chǎn)品目錄繪圖： 28-TSSOP
標(biāo)準(zhǔn)包裝： 1
類型： 分?jǐn)?shù) N 合成器
PLL： 是
輸入： 時(shí)鐘，晶體
輸出： 時(shí)鐘，晶體
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.1GHz
除法器/乘法器： 是/無(wú)
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.173"，4.40mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 28-TSSOP 裸露焊盤
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 587 (CN2011-ZH PDF)
其它名稱： 863-1076-6
DATA SHEET SKY72300-21 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
8
September 11, 2009 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice 101217N
Case 1: To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum
divide ratio is 32, the reference frequency (Fdiv_ref) must be a maximum of 12.5 MHz. Choosing a reference
frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore:
Ninteger
=
Fvco_aux
Fdiv_ref
=
400
8
=
50
The value to be programmed in the Auxiliary Divider Register is:
Nreg = Ninteger – 32
= 50 – 32
= 18 (decimal)
= 000010010 (binary)
Summary:
Auxiliary Divide Register = 0 0001 0010
C1416
Figure 5. Integer-N Applications: Sample Calculation
Normal Register Write. A normal 16-bit serial interface write
occurs when the CS signal is 16 clock cycles wide. The
corresponding 16-bit modulation data is simultaneously
presented to the Data pin. The content of the Modulation Data
Register is passed to the modulation unit at the next falling edge
of the divided main VCO frequency (Fpd_main).
Short CS Through Data Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented to the Data pin. The Data
pin is the default pin used to enter modulation data directly in the
Modulation Data Register with shortened CS strobes.
This method of data entry eliminates the register address
overhead on the serial interface. All serial interface bits are re-
synchronized internally at the reference oscillator frequency. The
content of the Modulation Data Register is passed to the
modulation unit at the next falling edge of the divided main VCO
frequency (Fpd_main).
Short CS Through Mod_in Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented on the Mod_in pin, an
alternate pin used to enter modulation data directly into the
Modulation Data Register with shortened CS strobes. This mode is
selected through the Modulation Control Register.
This method of data entry also eliminates the register address
overhead on the serial interface and allows a different device than
the one controlling the channel selection to enter the modulation
data (e.g., a microcontroller for channel selection and a digital
signal processor for modulation data).
All serial interface bits are internally re-synchronized at the
reference oscillator frequency and the content of the Modulation
Data Register is passed to the modulation unit at the next falling
edge of the divided main VCO frequency (Fpd_main).
Modulation data samples in the Modulation Data Register can be
from 2 to 12 bits long, and enable the user to select how many
distinct frequency steps are to be used for the desired modulation
scheme.
The user can also control the frequency deviation through the
modulation data magnitude offset in the Modulation Control
Register. This allows shifting of the modulation data to
accomplish a 2m multiplication of frequency deviation.
NOTE: The programmable range of –0.5 to +0.5 of the main
modulator can be exceeded up to the condition where
the sum of the dividend and the modulation data conform
to:
5625
.
0
)
dividend
N
(
5625
.
0
mod
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