參數(shù)資料
型號： SiI3114CTU
廠商： Silicon Image, Inc.
英文描述： PCI to Serial ATA Controller
中文描述： PCI到Serial ATA控制器
文件頁數(shù)： 40/127頁
文件大?。?/td> 598K
代理商： SII3114CTU
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI
-DS-0103-D
32
2007 Silicon Image, Inc.
Capabilities Pointer
Address Offset: 34
H
Access Type: Read
Reset Value: 0x0000_0060
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Capabilities Pointer
This register defines the link to a list of new capabilities associated with the PCI bus. The register bits are defined
below.
Bit [31:08]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:00]
: Capabilities Pointer (R) – Capabilities Pointer. This bit field defaults to 60
H
to define the
address for the 1
st
entry in a list of PCI Power Management capabilities.
Max Latency – Min Grant – Interrupt Pin – Interrupt Line
Address Offset: 3C
H
Access Type: Read/Write
Reset Value: 0x0000_0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Max Latency
Min Grant
Interrupt Pin
Interrupt Line
This register defines the various control functions associated with the PCI bus. The register bits are defined
below.
Bit [31:24]
: Max Latency (R) – Maximum Latency. This bit field is hardwired to 00
H
.
Bit [23:16]
: Min Grant (R) – Minimum Grant. This bit field is hardwired to 00
H
.
Bit [15:08]
: Interrupt Pin (R) – Interrupt Pin Used. This bit field is hardwired to 01
H
to indicate that the
SiI
3114 uses the INTA# interrupt.
Bit [07:00]
: Interrupt Line (R/W) – Interrupt Line. This bit field is used by the system to indicate interrupt
line routing information. The
SiI
3114 does not use this information.
Configuration
Address Offset: 40
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
B
P
This register defines the various control functions associated with the PCI bus. The register bits are defined
below.
Bit [31:02]
: Reserved (R). This bit field is hardwired to 00000000
H
.
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參數(shù)描述
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