參數(shù)資料
型號: SI5369-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 80/84頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5369 CLK MULT
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,精密時鐘
嵌入式:
已用 IC / 零件: Si5369
已供物品: 板,線纜,CD,文檔
Si5369
Rev. 1.0
81
Table 12. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e0.50 BSC.
E
15.40 REF.
D
15.40 REF.
E2
3.90
4.10
D2
3.90
4.10
GE
13.90
GD
13.90
X
0.30
Y1.50 REF.
ZE
16.90
ZD
16.90
R1
0.15 REF
R2
1.00
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
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