參數(shù)資料
型號(hào)： SI5338N-AXXXXXGM
廠(chǎng)商： SILICON LABORATORIES
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
封裝： 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件頁(yè)數(shù)： 6/42頁(yè)
文件大?。?/td> 380K
代理商： SI5338N-AXXXXXGM
Si5338
14
Rev. 1.0
Table 13. Typical Phase Noise Performance
Offset Frequency
25 MHz XTAL
to 156.25 MHz
27 MHz Ref In
to 148.3517 MHz
19.44 MHz Ref In
to 155.52 MHz
Units
100 Hz
–90
–87
–110
dBc/Hz
1 kHz
–120
–117
–116
dBc/Hz
10 kHz
–126
–123
dBc/Hz
100 kHz
–132
–130
–128
dBc/Hz
1 MHz
–132
–128
dBc/Hz
10 MHz
–145
dBc/Hz
Table 14. I2C Specifications (SCL,SDA)1
Parameter
Symbol
Test Condition
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
LOW Level
Input Voltage
VILI2C
–0.5
0.3 x VDDI2
C
–0.5
0.3 x VDDI2C
V
HIGH Level
Input Voltage
VIHI2C
0.7 x VDDI2
C
3.63
0.7 x VDDI2C
3.63
V
Hysteresis of
Schmitt Trigger
Inputs
VHYS
N/A
0.1
—
V
LOW Level Out-
put Voltage
(open drain or
open collector)
at 3 mA Sink
Current
VOLI2C
VDDI2C
2 = 2.5/3.3 V
0
0.4
0
0.4
V
VDDI2C
2 = 1.8 V
N/A
0
0.2 x VDDI2C
V
Input Current
II2C
–10
10
–10
10
A
Capacitance for
each I/O Pin
CI2C
VIN = –0.1 to VDDI2C
—4
—
4
pF
I2C Bus Time-
out
—
Timeout Enabled
25
35
25
35
ms
Data Rate
Standard Mode
100
400
kbps
Notes:
1. Refer to NXP’s UM10204 I2C-bus specification and user manual, Revision 03, for further details:
2. I2C pullup voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I2C bus voltage is less
than 2.5 V to maintain compatibility with the I2C bus standard.
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