參數(shù)資料
型號(hào): SI5338N-AXXXXXGM
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
封裝: 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件頁數(shù): 29/42頁
文件大小: 380K
代理商: SI5338N-AXXXXXGM
Si5338
Rev. 1.0
35
8. Device Pinout by Part Number
The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock
frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/
M/Q have a maximum output clock frequency of 200 MHz.
Devices are also orderable according to the pin control functions available on Pins 3 and 4:
CLKIN—single-ended clock input
I2C_LSB—determines the LSB bit of the 7-bit I2C address
FINC—frequency increment pin
FDEC—frequency decrement pin
PINC—phase increment pin
PDEC—phase decrement pin
FDBK—single-ended feedback input
OEB—output enable
Table 16. Pin Function by Part Number
Pin #
Si5338A: 710 MHz
Si5338B: 350 MHz
Si5338C: 200 MHz
Si5338D: 710 MHz
Si5338E: 350 MHz
Si5338F: 200 MHz
Si5338G: 710 MHz
Si5338H: 350 MHz
Si5338J: 200 MHz
Si5338K: 710 MHz
Si5338L: 350 MHz
Si5338M: 200 MHz
Si5338N: 710 MHz
Si5338P: 350 MHz
Si5338Q: 200 MHz
1CLKIN1
CLKIN1
CLKIN1
CLKIN1
2CLKINB1
CLKINB1
CLKINB1
CLKINB1
3CLKIN2
PINC
FINC
OEB
CLKIN2
4
I2C_LSB
PDEC
FDEC
I2C_LSB
5FDBK4
FDBK4
FDBK4
FDBK4
6FDBKB4
FDBKB4
FDBKB4
7
VDD
8
INTRINTRINTRINTRINTR
9
CLK3B
10
CLK3A
11
VDDO3
12
SCL
13
CLK2B
14
CLK2A
15
VDDO2
16
VDDO1
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
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