參數(shù)資料
型號(hào): SI5338N-A00000-GMR
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
封裝: 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件頁數(shù): 15/34頁
文件大?。?/td> 285K
代理商: SI5338N-A00000-GMR
Si5338
22
Rev. 0.5
synthesis to achieve complex frequency translations.
Examples are in broadcast video (e.g. 148.5 MHz to
148.351648351648 MHz), WAN/LAN applications (e.g.
155.52 MHz
to
156.25 MHz),
and
Forward
Error
Correction (FEC) applications (e.g. 156.25 MHz to
161.1328125 MHz). Using the input reference selectors,
the Si5338 can select from one of four inputs (IN1/IN2,
IN3, IN4, IN5/IN6). Figure 16 shows the Si5338
configured as a synchronous clock generator.
Figure 16. Si5338 as a Synchronous Clock
Generator or Frequency Translator
4.3. Configurable Buffer and Level
Translator
Using the output selectors, the synthesis stage can be
entirely bypassed allowing the Si5338 to act as a
configurable clock buffer/divider with level translation
and selectable inputs. Because of its highly selectable
configuration, virtually any combination is possible. The
configurable
output
drivers
allow
four
differential
outputs, eight single-ended outputs, or a combination of
both. Figure 17 shows the Si5338 configured as a
flexible clock buffer.
Figure 17. Si5338 as a Configurable Clock
Buffer/Divider with Level Translation
4.3.1. Combination Free-Running and Synchronous
Clock Generator
Another application of the Si5338 is in generating both
free-running and synchronous clocks in one device.
This is accomplished by configuring the input and
output selectors for the desired split configuration. An
example of such an application is shown in Figure 18.
Figure 18. Si5338 In a Free-Running and
Synchronous Clock Generator Application
M0
R0
Si5338
F0
F1
F2
F3
M1
R1
M2
M3
R2
R3
P1
P2
PLL
ref
Fin
R0
Si5338
R1
R2
R3
Fin
Fin *
1
R0
Fin *
1
R1
Fin*
1
R2
Fin *
1
R3
R0
F0
F1
F2
F3
R1
M0
M1
R2
R3
P2
Si5338
Osc
XTAL
PLL
ref
Fin
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