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參數(shù)資料
| 型號： | SI5338N-A00000-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 285K |
| 代理商： | SI5338N-A00000-GMR |
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Si5338
20
Rev. 0.5
3.7. Output Enable
There two methods of enabling and disabling the output
drivers: Pin control, and I2C control.
3.7.1. Enabling Outputs Using Pin Control
The Si5338K/L/M devices provide an Output Enable pin
(OEB) as shown in Figure 11. Pulling this pin high will
tri-state all four output drivers.
Figure 11. Output Enable Pin (Si5338K/L/M)
3.7.2. Enabling Outputs Through the I2C Interface
Output enable can be controlled through the I2C
interface. As shown in Figure 12, register 230[3:0]
allows control of each individual output driver. Register
230[4] controls all drivers at once. Registers 110[7:6],
114[7:6], 118[7:6], 112[7:6] control the output disabled
state as tri-state, low, high, or always on.
Figure 12. Output Enable Control Registers
3.8. Useful Features of the Si5338
The Si5338 offers several features and functions which
are useful in many timing applications. The following
paragraphs describes the main features in detail and
typical applications.
3.8.1. Frequency Increment/Decrement
Each
of
the
output
clock
frequencies
can
be
independently stepped up or down in pre-defined steps
as low as 1 ppm per step. Setting of the step size and
control of the frequency increment or decrement is
accomplished through the I2C interface. Alternatively,
the Si5338 can be ordered with optional frequency
increment (FINC) and frequency decrement (FDEC)
pins for pin controlled applications. See Table 15 for
ordering information of pin controlled devices.
The frequency increment and decrement feature is
useful in applications that require a variable clock
frequency (e.g. CPU speed control, FIFO overflow
management, etc...) or in applications where frequency
margining (e.g. fout+/-5%) is necessary for design
verification and manufacturing test. Frequency steps
are seamless and glitchless.
3.8.2. Output Phase Increment/Decrement
The Si5338 has a digitally-controlled glitchless phase
increment and decrement feature that allows adjusting
the phase of each output clock in relation to the other
output clocks. The phase of each output clock can be
adjusted with an accuracy of 20 ps over a range of +/-
45 ns. Setting of the step size and control of the phase
increment or decrement is accomplished through the
I2C interface. Alternatively, the Si5338 can be ordered
with optional phase increment (PINC) and frequency
decrement (PDEC) pins for pin controlled applications.
See Table 15 for ordering information of pin controlled
devices.
The phase increment and decrement feature provides a
useful method for fine tuning set-up and hold timing
margins or adjusting for mismatched PCB trace lengths.
3.8.3. Zero-Delay Buffer/Clock Generator Mode
The Si5338 supports an optional zero delay mode of
operation for applications that require minimal input-to-
output delay. In this mode, one of the device output
clocks is fed back to the feedback input pin (IN4 or IN5/
IN6) to implement an external feedback path essentially
nullifying the delay between the reference input and the
output clocks. Figure 13 shows the Si5338 in a typical
zero delay buffer configuration. The zero-delay mode
combined with the phase increment/decrement feature
allows unprecedented flexibility in generating clocks
with precise edge alignment.
OEB
Control
NVM
(OTP)
RAM
0 = Enabled
1 = Disabled
230
OEB
0
OEB
1
OEB
2
OEB
3
OEB
All
1
2
3
4
5
6
7
0 = enable
1 = disable
110
0
1
2
3
4
5
6
7
CLK0 OEB
State
114
0
1
2
3
4
5
6
7
CLK1 OEB
State
118
0
1
2
3
4
5
6
7
CLK2 OEB
State
122
0
1
2
3
4
5
6
7
CLK3 OEB
State
00 = disabled tri-state
01 = disabled low
10 = disabled high
11 = always enabled
Bits reserved
Bits used by other functions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338N-A00211-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338N-A01659-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-A01659-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| Si5338N-A-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-prgrmmbl clock generatr .16-700 MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338N-A-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-710MHz 4Clk In RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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