(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%," />
參數(shù)資料
型號: SI5322/23-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 23/24頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5322/23
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5322,SI5323
已供物品: 板,線纜,CD,文檔
Si5322
8
Rev. 0.51
Table 3. AC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
CKIN Input Pins
Input Frequency
CKNF
19.44
707.35
MHz
Input Duty Cycle
(Minimum Pulse Width)
CKNDC
Whichever is smaller
(i.e., the 40%/60% limitation
applies only to high clock
frequencies)
40
60
%
2—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
CKOUTn Output Pins
Output Frequency (Output not
configured for CMOS or disable)
CKOF
19.44
1050
MHz
Maximum Output Frequency in
CMOS Format
CKOFMC
212.5
MHz
Single-ended Output Rise/Fall
(20–80%)
CKOTRF
CMOS Output
VDD =1.71
Cload = 5 pF
——
8
ns
CMOS Output
VDD =2.97
Cload = 5 pF
——
2
ns
Differential Output Rise/Fall Time
CKOTRF
20 to 80 %, fOUT = 622.08
230
350
ps
Output Duty Cycle Differential
Uncertainty
CKODC
100
Load
Line to Line
Measured at 50% Point
(not for CMOS)
——
±40
ps
LVCMOS Input Pins
Minimum Reset Pulse Width
tRSTMIN
1—
s
Input Capacitance
CIN
——
3
pF
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD =20pf
—25
ns
LOSn Trigger Window
LOSTRIG
From last CKIN
to LOS
—750
s
PLL Performance
Output Clock Phase Change
tP_STEP
After clock switch
f3
128 kHz
—200
ps
Closed Loop Jitter Peaking
JPK
0.05
0.1
dB
Jitter Tolerance
JTOL
BW determined by
BWSEL[1:0]
5000/
BW
ns pk-
pk
Spurious Noise
SPSPUR
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
–93
–70
dBc
Phase Change due to Temperature
Variation
tTEMP
Max phase changes from –
40 to +85 C
300
500
ps
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