(VDD
參數(shù)資料
型號: SI5322/23-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 19/24頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI5322/23
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: SI5322,SI5323
已供物品: 板,線纜,CD,文檔
Si5322
4
Rev. 0.51
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Temperature Range
TA
–40
25
85
C
Supply Voltage
VDD
3.3 V nominal
2.97
3.3
3.63
V
2.5 V nominal
2.25
2.5
2.75
V
1.8 V nominal
1.71
1.8
1.89
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current
(Supply current is indepen-
dent of VDD)
IDD
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled1
251
279
mA
LVPECL Format
622.08 MHz Out
Only 1 CKOUT Enabled1
217
243
mA
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
204
234
mA
CMOS Format
19.44 MHz Out
Only CKOUT1 Enabled
194
220
mA
CKIN Input Pins
Input Common Mode
Voltage
(Input Threshold Voltage)
VICM
1.8 V ±5%
0.9
1.4
V
2.5 V ±10%
1.0
1.7
V
3.3 V ±10%
1.1
1.95
V
Input Resistance
CKNRIN
Single-ended
20
40
60
k
Input Voltage Level Limits
CKNVIN
See Note 2
0—
VDD
V
Single-Ended Input Voltage
Swing
VISE
fCKIN < 212.5 MHz
0.2
VPP
fCKIN > 212.5 MHz
0.25
VPP
Notes:
1. LVPECL outputs require nominal VDD > 2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
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