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參數(shù)資料
| 型號： | SI5110-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99LFBGA |
| 標準包裝： | 168 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應商設備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Si5110
Rev. 1.5
25
17. Pin Descriptions: Si5110
Pin
Number(s)
Name
I/O
Signal Level
Description
H3
H6
BWSEL1
BWSEL0
I
LVTTL
Transmit DSPLL Bandwidth Select.
The inputs select loop bandwidth of the Transmit
Clock Multiplier DSPLL as listed in Table 6.
Note: Both inputs have an internal pulldown.
H7
DLBK
I
LVTTL
Diagnostic Loopback.
When this input is low, the transmit clock and data are
looped back for output on RXDOUT, RXCLK1 and
RXCLK2. This pin should be held high for normal
operation.
Note: This input has an internal pullup.
J5
FIFOERR
O
LVTTL
FIFO Error.
This output is asserted (driven low) when a FIFO over-
flow/underflow has occurred. This output is low until
reset by asserting FIFORST.
H5
FIFORST
I
LVTTL
FIFO RESET.
When this input is low, the read/write FIFO pointers
are reset to their initial state.
Note: This input has an internal pullup.
B2, C2, D1,
E2, E7–9,
F2, F7–9,
G1, H2, J2,
K1
GND
Supply Ground.
Connect to system GND. Ensure a very low
impedance path for optimal performance.
H8
LLBK
I
LVTTL
Line Loopback.
When this input is low, the recovered clock and data
are looped back for output on TXDOUT, and TXCLK-
OUT. Set this pin high for normal operation.
Note: This input has an internal pullup.
D2
LOS
O
LVTTL
Loss-of-Signal.
This output is asserted (driven low) when the peak-to-
peak signal amplitude on RXDIN is below the thresh-
old set via LOSLVL.
B3
LOSLVL
I
LOS Threshold Level.
Applying an analog voltage to this pin allows adjust-
ment of the Threshold used to declare LOS. Tieing
this input to VREF disables LOS detection and forces
the LOS output high.
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