參數(shù)資料
型號： SI5110-H-BL
廠商： Silicon Laboratories Inc
文件頁數(shù)： 7/36頁
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH LP HS 99-PBGA
標(biāo)準(zhǔn)包裝： 168
系列： SiPHY™
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： SONET/SDH
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
封裝/外殼： 99-LBGA
供應(yīng)商設(shè)備封裝： 99-BGA（11x11）
包裝： 托盤
Si5110
Rev. 1.5
15
reacquisition, the recovered clock frequency (RXCLK1
and RXCLK2) drifts over a range of approximately
±1000 ppm relative to the supplied reference clock
unless LTR is asserted. The RXLOL output remains
asserted until the frequency of the (divided) recovered
clock differs from the reference clock frequency by less
than the amount specified in Table 5 on page 9.
The RXLOL output will be asserted automatically if a
valid reference clock is not detected.
The RXLOL output will also be asserted whenever the
loss of signal alarm (LOS) is active, provided that the
LTR input is set high (i.e., provided that the device is not
configured for Lock-to-Reference mode).
5.3.3. Lock-to-Reference
The lock-to-reference (LTR) input can be utilized to
ensure the presence of a stable output clock during a
loss-of-signal alarm (LOS). When LTR is asserted, the
CDR is prevented from phase locking to the data signal
and the CDR locks the RXCLKOUT1 and RXCLKOUT2
outputs to the reference clock. In typical applications,
the LOS output is tied to the LTR input to force a stable
output clock during a loss-of-signal condition.
5.4. Deserialization
The Si5110 uses a 1:4 demultiplexer to deserialize the
high-speed input. The deserialized data is output on a
4-bit parallel data bus, RXDOUT[3:0], aligned with the
rising edge of RXCLK1.
5.4.1. Serial Input to Parallel Output Relationship
The Si5110 provides the capability to select the order in
which the received serial data is mapped to the parallel
output bus RXDOUT[3:0]. The mapping of the receive
bits to the output data word is controlled by the
RXMSBSEL input. When RXMSBSEL is set low, the
first bit received is output on RXDOUT0, and the
following bits are output in order on RXDOUT1 through
RXDOUT3. When RXMSBSEL is set high, the first bit
received is output on RXDOUT3, and the following bits
are output in order on RXDOUT2 through RXDOUT0.
5.5. Voltage Reference Output
The Si5110 provides an output voltage reference that
can be used by external circuitry to set the LOS
threshold, slicing level, or sampling phase adjustment
input voltage levels. One possible implementation uses
a resistor divider to set the control voltage for the
LOSLVL,
SLICELVL,
or
PHASEADJ
inputs.
An
alternative is the use of digital-to-analog converters
(DACs) to set the control voltages. Using this approach,
VREF is used to set the range of the DAC outputs. The
voltage on the VREF output is nominally 1.25 V.
Figure 4. Typical LOSLVL Transfer Curve, Absolute Slice Mode (SLICEMODE = 0)
0
50
100
150
200
250
300
350
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
LOSLV (V)
V
LOS
(mV)
Assert
DeAssert
V L
O
S
=
.9
58
LO
SL
VL
V LO
S
= .
76
2 L
OS
LV
L
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