- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9967 > SI5110-H-BL (Silicon Laboratories Inc)IC TXRX SONET/SDH LP HS 99-PBGA PDF資料下載
參數(shù)資料
| 型號： | SI5110-H-BL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99-PBGA |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應(yīng)商設(shè)備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
Si5110
Rev. 1.5
25
17. Pin Descriptions: Si5110
Pin
Number(s)
Name
I/O
Signal Level
Description
H3
H6
BWSEL1
BWSEL0
I
LVTTL
Transmit DSPLL Bandwidth Select.
The inputs select loop bandwidth of the Transmit
Clock Multiplier DSPLL as listed in Table 6.
Note: Both inputs have an internal pulldown.
H7
DLBK
I
LVTTL
Diagnostic Loopback.
When this input is low, the transmit clock and data are
looped back for output on RXDOUT, RXCLK1 and
RXCLK2. This pin should be held high for normal
operation.
Note: This input has an internal pullup.
J5
FIFOERR
O
LVTTL
FIFO Error.
This output is asserted (driven low) when a FIFO over-
flow/underflow has occurred. This output is low until
reset by asserting FIFORST.
H5
FIFORST
I
LVTTL
FIFO RESET.
When this input is low, the read/write FIFO pointers
are reset to their initial state.
Note: This input has an internal pullup.
B2, C2, D1,
E2, E7–9,
F2, F7–9,
G1, H2, J2,
K1
GND
Supply Ground.
Connect to system GND. Ensure a very low
impedance path for optimal performance.
H8
LLBK
I
LVTTL
Line Loopback.
When this input is low, the recovered clock and data
are looped back for output on TXDOUT, and TXCLK-
OUT. Set this pin high for normal operation.
Note: This input has an internal pullup.
D2
LOS
O
LVTTL
Loss-of-Signal.
This output is asserted (driven low) when the peak-to-
peak signal amplitude on RXDIN is below the thresh-
old set via LOSLVL.
B3
LOSLVL
I
LOS Threshold Level.
Applying an analog voltage to this pin allows adjust-
ment of the Threshold used to declare LOS. Tieing
this input to VREF disables LOS detection and forces
the LOS output high.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX11642EEG+T | IC ADC 8BIT 8CH 24QSOP |
| IDT723636L15PF8 | IC FIFO SYNC 512X36X2 128QFP |
| MS27473E20A41SB | CONN PLUG 41POS STRAIGHT W/SCKT |
| MS27472T10A13PA | CONN RCPT 13POS WALL MT W/PINS |
| SI5110-H-GL | IC TXRX SONET/SDH LP HS 99LFBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5110-H-GL | 功能描述:電信線路管理 IC OC-48 STM-16 SONET SDH Trnscvr 1:16 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI5110-H-XL4 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI5110-H-ZL3 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI511BBA200M000BAGR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI511BBA200M000BAGR OSC (200MHZ) |
| SI51210 | 制造商:SILABS 制造商全稱:SILABS 功能描述:TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。