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參數(shù)資料
| 型號： | SI5110-H-BL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99-PBGA |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應(yīng)商設(shè)備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Si5110
20
Rev. 1.5
10. Bias Generation Circuitry
The Si5110 uses two external resistors, RXREXT and
TXREXT, to set internal bias currents for the receive
and transmit sections of the device, respectively. The
external resistors allow precise generation of bias
currents,
which
can
significantly
reduce
power
consumption. The bias generation circuitry requires two
3.09 k
(1%) resistors each connected between
RXREXT and GND, and between TXREXT and GND.
11. Reference Clock
The Si5110 supports operation with one of two possible
reference clock sources. In the first configuration, an
external reference clock is connected to the REFCLK
input. The second configuration uses the parallel data
clock, TXCLK4IN, as the reference clock source. The
REFSEL input is used to select whether the REFCLK or
the TXCLK4IN input will be used as the reference clock.
When REFCLK is selected as the reference clock
source (REFSEL = 1), two possible reference clock
frequencies
are
supported.
The
reference
clock
frequency provided on the REFCLK input can be either
1/16th or 1/32nd the desired transceiver data rate. The
REFCLK frequency is selected using the REFRATE
input.
The TXCLK4IN clock frequency is equal to 1/4th the
transceiver data rate. When TXCLK4IN is selected as
the
reference
clock
source
(REFSEL = 0),
the
REFRATE input has no effect.
The CMU in the Si5110’s transmit section multiplies the
provided reference up to the serial transmit data rate.
When the CMU has achieved lock with the selected
reference, the TXLOL output is deasserted (driven
high).
The CDR in the receive section of the Si5110 uses the
selected reference clock to center the receiver PLL
frequency in order to speed lock acquisition. When the
receive CDR locks to the data input, the RXLOL signal
is deasserted (driven high).
12. Reset
The Si5110 is reset by holding the RESET pin low for at
least 1 s. When RESET is asserted, the input FIFO
pointers are reset and the digital control circuitry is
initialized.
When RESET transitions high to start normal operation,
the transmit CMU calibration is performed.
13. Transmit Differential Output
Circuit
The Si5110
utilizes a current-mode
logic
(CML)
architecture to drive the high-speed serial output clock
and data on TXCLKOUT and TXDOUT. An example of
output termination with ac coupling is shown in Figure 9.
In applications where direct dc coupling is possible, the
0.1
F capacitors may be omitted. The differential peak-
to-peak voltage swing of the CML architecture is listed
14. Internal Pullups and Pulldowns
On-chip 30 k
resistors are used to individually set the
LVTTL inputs if these inputs are left disconnected. The
specific default state of each input is enumerated in 17.
15. Power Supply Filtering
The transmitter generated jitter is most sensitive to
power supply noise below its PLL loop-bandwidth
(BWSEL setting). The power supply noise of interest is
bounded between the SONET/SDH generated jitter
specification of 12 kHz (for 2.48832 Gbps) and the PLL
loop-bandwidth. Integrated supply noise from 1/10th the
SONET/SDH specification (1.2 kHz) to 10x the loop-
bandwidth should be suppressed to a level appropriate
for each design. Below the PLL loop-bandwidth, the
typical
generated
jitter
due
to
supply
noise
is
approximately 2.5 mUIpp per 1 mVrms; this parameter
can be used as a guideline for calculating the output
jitter and supply filtering requirements. The receiver
does not place additional power supply constraints
beyond those listed for the transmitter.
Please
contact
Silicon
Laboratories’
applications
engineering for recommendations on bypass capacitors
and their placement.
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