參數(shù)資料
型號(hào): SI5100-H-BL
廠商: Silicon Laboratories Inc
文件頁數(shù): 27/40頁
文件大?。?/td> 0K
描述: IC TXRX SONET/SDH LP HS 195-PBGA
標(biāo)準(zhǔn)包裝: 119
系列: SiPHY™
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: SONET/SDH
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
封裝/外殼: 195-LBGA
供應(yīng)商設(shè)備封裝: 195-BGA(15x15)
包裝: 托盤
Si5100
Rev. 1.5
33
J13
K13
J14
K14
L13
M13
L14
M14
N14
N13
P14
P13
N12
N11
P12
P11
N10
N9
P10
P9
N8
N7
P8
P7
N6
N5
P6
P5
N4
N3
P4
P3
TXDIN15+
TXDIN15–
TXDIN14+
TXDIN14–
TXDIN13+
TXDIN13–
TXDIN12+
TXDIN12–
TXDIN11+
TXDIN11–
TXDIN10+
TXDIN10–
TXDIN9+
TXDIN9–
TXDIN8+
TXDIN8–
TXDIN7+
TXDIN7–
TXDIN6+
TXDIN6–
TXDIN5+
TXDIN5–
TXDIN4+
TXDIN4–
TXDIN3+
TXDIN3–
TXDIN2+
TXDIN2–
TXDIN1+
TXDIN1–
TXDIN0+
TXDIN0–
ILVDS
Differential Parallel Transmit Data Input.
The 4-bit or 16-bit data word present on these
pins is multiplexed into a high-speed serial
stream and output on TXDOUT. The data word
size is set by the MODE16 input. The bit order
for transmit multiplexing is selected by the
TXMSBSEL input. The data on TXDIN[15:0] is
clocked into the device by the rising edge of
TXCLK16IN.
K1
L1
TXDOUT+
TXDOUT–
OCML
Differential High-Speed Transmit Data
Output.
The 4-bit or 16-bit word input on TXDIN[15:0] is
multiplexed into a high-speed serial stream that
is output on the TXDOUT pins. The data word
size is set by the MODE16 input. The bit order
for transmit multiplexing is selected by the
TXMSBSEL input. The TXDOUT outputs are
updated by the rising edge of TXCLKOUT.
M5
TXLOL
O
LVTTL
Transmit CMU Loss-of-Lock.
The TXLOL output is asserted (low) when the
CMU is not phase-locked to the selected refer-
ence source or if REFCLK is not present. See
Pin Number(s)
Name
I/O
Signal Level
Description
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