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參數資料
| 型號： | SI5100-H-BL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 19/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 195-PBGA |
| 標準包裝： | 119 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 195-LBGA |
| 供應商設備封裝： | 195-BGA（15x15） |
| 包裝： | 托盤 |
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Si5100
26
Rev. 1.5
17. Pin Descriptions: Si5100
Alphabetically listed by name
Pin Number(s)
Name
I/O
Signal Level
Description
M10
M7
BWSEL1
BWSEL0
I
LVTTL
Transmit DSPLL Bandwidth Select.
The inputs select loop bandwidth of the Transmit
Clock Multiplier DSPLL as listed in Table 6.
Note: Both inputs have an internal pulldown.
F12
DLBK
I
LVTTL
Diagnostic Loopback.
When this input is low, the transmit clock and
data are looped back for output on RXDOUT,
RXCLK1 and RXCLK2. This pin should be held
high for normal operation.
Note: This input has an internal pullup.
K3
FIFOERR
O
LVTTL
FIFO Error.
This output is asserted (driven low) when a FIFO
overflow/underflow has occurred. This output is
low until reset by asserting FIFORST.
M6
FIFORST
I
LVTTL
FIFO RESET.
When this input is low, the read/write FIFO point-
ers are reset to their initial state.
Note: This input has an internal pullup.
B1, C1–2, D2,
D5–11, E4, E11,
E2, F11, F1–2,
G11, G2, H11,
H2, J11, J1–4,
K11, K2, L5–11,
L2, M1–4
GND
Supply Ground.
Connect to system GND. Ensure a very low
impedance path for optimal performance.
H12
LLBK
I
LVTTL
Line Loopback.
When this input is low, the recovered clock and
data are looped back for output on TXDOUT,
and TXCLKOUT. Set this pin high for normal
operation.
Note: This input has an internal pullup.
G3
LOS
O
LVTTL
Loss-of-Signal.
This output is asserted (driven low) when the
peak-to-peak signal amplitude on RXDIN is
below the threshold set via LOSLVL.
C3
LOSLVL
I
LOS Threshold Level.
Applying an analog voltage to this pin allows
adjustment of the Threshold used to declare
LOS. Tieing this input to VREF disables LOS
detection and forces the LOS output high.
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