參數(shù)資料
型號(hào): SI5023
廠商: Electronic Theatre Controls, Inc.
元件分類: 運(yùn)動(dòng)控制電子
英文描述: MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP
中文描述: 多速率SONET / SDH的CDR集成電路限幅放大器
文件頁數(shù): 19/22頁
文件大?。?/td> 399K
代理商: SI5023
Si5022/Si5023
Preliminary Rev. 0.46
19
19
RESET/CAL
I
LVTTL
Reset/Calibrate.
Driving this input high for at least 1
μ
S will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low. This pin should be
used to force a DSPLL calibration on power-up to
ensure optimal jitter performance.
Note:
This input has a weak internal pull-down.
External Bias Resistor.
This resistor is used to establish internal bias cur-
rents within the device. This pin must be connected
to GND through a 10 k
(
1
%)
resistor.
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note:
This input has a weak internal pull-down.
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. The applied voltage is mapped to
one of 64 BER threshold levels. When the BER
exceeds the programmed threshold, BER_ALM is
driven low. If this pin is tied to GND, BER_ALM is
disabled. If it is tied to V
DD
, BER_LVL defaults to
10
–3
BER
Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded. The
alarm will clear after the BER rate has improved by
approximately a factor of 2.
No Connect.
Leave this pin unconnected.
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 28-lead micro leaded package (see
Figure 14) must be connected directly to supply
ground. Minimize the ground path inductance for
optimal performance.
20
REXT
22,23
CLKOUT–,
CLKOUT+
O
CML
24
CLKDSBL
I
LVTTL
26
BER_LVL
I
27
BER_ALM
O
LVTTL
28
NC
GND Pad
GND
GND
Table 9. Si5022/23 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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