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參數(shù)資料
| 型號： | SI5020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC |
| 中文描述： | SiPHY多速率SONET / SDH的時鐘和數(shù)據(jù)恢復(fù)芯片 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 335K |
| 代理商： | SI5020 |
Si5020
8
Preliminary Rev. 0.8
Table 4. AC Characteristics (PLL Characteristics)
(V
A
2.5 V ± 5%, T
A
= –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
(OC-48)*
J
TOL(P–P)
f = 600 Hz
f = 6000 Hz
f = 100 kHz
f = 1 MHz
f = 30 Hz
f = 300 Hz
f = 25 kHz
f = 250 kHz
f = 30 Hz
f = 300 Hz
f = 6.5 kHz
f = 65 kHz
40
4
4
0.4
40
4
4
0.4
60
6
6
0.6
600
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
—
—
—
—
—
—
—
—
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
ps
Jitter Tolerance (OC-12 Mode)
*
J
TOL(P–P)
Jitter Tolerance (OC-3 Mode)
*
J
TOL(P–P)
Jitter Tolerance (Gigabit Ethernet)
Receive Data Total Jitter
Tolerance
Jitter Tolerance (Gigabit Ethernet)
Receive Data Deterministic Jitter
Tolerance
RMS Jitter Generation
*
Peak-to-Peak Jitter Generation
*
Jitter Transfer Bandwidth
*
T
JT(P-P)
IEEE 802.3z Clause 38.68
D
JT(P-P)
IEEE 802.3z Clause 38.69
370
TBD
—
ps
J
GEN(rms)
J
GEN(rms)
J
BW
with no jitter on serial data
with no jitter on serial data
OC-48 Mode
OC-12 Mode
OC-3 Mode
—
—
—
—
—
—
1.45
3.0
25
—
—
—
0.03
1.5
5.0
55
2.0
500
130
0.1
1.7
mUI
mUI
MHz
kHz
kHz
dB
ms
Jitter Transfer Peaking
*
Acquisition Time
J
P
T
AQ
After falling edge of
PWRDN/CAL
From the return of valid
data
40
60
150
μ
s
Input Reference Clock Duty Cycle
Reference Clock Range
Input Reference Clock Frequency
Tolerance
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
Frequency Difference at which
Receive PLL goes into Lock (REF-
CLK compared to the divided
down VCO clock)
*Note:
Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 2
23
– 1 data pattern.
C
DUTY
40
50
—
—
60
%
19.44
–100
168.75
100
MHz
ppm
C
TOL
LOL
TBD
600
TBD
ppm
LOCK
TBD
300
TBD
ppm
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